# Verilog

## [Semaine 1](/Semaine_1/) 

## [Semaine 2](/Semaine_2/)


## Cheat sheet
### Commands
Compile code
iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v


#### Upload on fpga
rem https://github.com/YosysHQ/apicula
yosys -p "read_verilog blink_led.v; synth_gowin -json blink_led_c.json"

set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k

nextpnr-himbaechel --json blink_led_c.json --write pnr_blink_led.json --device %DEVICE% --vopt cst=blink_led.cst --vopt family=GW2A-18C

gowin_pack -d %DEVICE% -o blink_led_c.fs pnr_blink_led.json

openfpgaloader -b %BOARD% blink_led_c.fs