module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	
    wire tand1;
    wire tand2;

    wire and1;
    wire and2;

    wire or1;
    wire or2;

    assign tand1 = p1a & p1b & p1c;
    assign tand2 = p1d & p1e & p1f;

    assign and1 = p2a & p2b;
    assign and2 = p2c & p2d;

    assign or1 = tand1 | tand2;
    assign or2 = and1 | and2;

    assign p1y = or1;
    assign p2y = or2;

endmodule