forked from tanchou/Verilog
39 lines
491 B
Coq
39 lines
491 B
Coq
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`timescale 1ns/1ps
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`default_nettype none
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module example1_tb ();
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reg clk = 0;
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initial forever #5 clk = !clk;
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wire strobe;
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example1 count (.clk(clk), .strobe(strobe));
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initial begin
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`ifdef VCD_DUMP
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$dumpfile("counter_tb.vcd");
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$dumpvars(0,example1_tb);
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`endif
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end
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initial begin
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`ifdef END_TIME
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#`END_TIME $finish();
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`else
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#1000 $finish();
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`endif
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end
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initial begin
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#500 $finish();
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end
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always @(posedge clk) begin
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if (strobe) $display("Strobe");
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end
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endmodule
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