verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity
Files
0faab53c30e5007cd569e8146dbee5ccd5b56e0d
Verilog_Louis/Semaine_3/UARTV3/tb_rx_tx.out

1093 lines
32 KiB
Plaintext
Raw Normal View History

uart v3
2025-05-02 11:03:14 +02:00
#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_00000154aa078310 .scope module, "tb_top_uart_rx_tx" "tb_top_uart_rx_tx" 2 3;
.timescale -9 -12;
L_00000154aa0b4200 .functor BUFZ 1, v00000154aa0bac90_0, C4<0>, C4<0>, C4<0>;
v00000154aa1235e0_0 .var "clk", 0 0;
v00000154aa124b20_0 .var "data_in", 7 0;
v00000154aa124d00_0 .var "read_fifo", 0 0;
v00000154aa123a40_0 .net "rx", 0 0, L_00000154aa0b4200; 1 drivers
v00000154aa123720_0 .net "rx_data", 7 0, v00000154aa0c9f20_0; 1 drivers
v00000154aa124bc0_0 .var "rx_data_ready", 0 0;
o00000154aa0cf0e8 .functor BUFZ 1, c4<z>; HiZ drive
v00000154aa124580_0 .net "rx_data_valid", 0 0, o00000154aa0cf0e8; 0 drivers
v00000154aa123d60_0 .net "tx", 0 0, v00000154aa0bac90_0; 1 drivers
v00000154aa125200_0 .var "tx_data_valid", 0 0;
E_00000154aa0c27c0 .event anyedge, v00000154aa123540_0;
S_00000154aa0a53f0 .scope module, "top_inst" "uart_top" 2 16, 3 1 0, S_00000154aa078310;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "uart_rx";
.port_info 3 /OUTPUT 1 "uart_tx";
.port_info 4 /OUTPUT 8 "rx_data";
.port_info 5 /OUTPUT 1 "rx_data_valid";
.port_info 6 /INPUT 1 "rx_data_ready";
.port_info 7 /INPUT 1 "read_fifo";
.port_info 8 /INPUT 8 "tx_data";
.port_info 9 /INPUT 1 "tx_data_valid";
.port_info 10 /OUTPUT 1 "tx_data_ready";
P_00000154aa0b68e0 .param/l "BAUD_RATE" 0 3 21, +C4<00000000000000011100001000000000>;
P_00000154aa0b6918 .param/l "CLK_FRE" 0 3 20, +C4<00000001100110111111110011000000>;
L_00000154aa0b3d30 .functor AND 1, L_00000154aa123f40, v00000154aa0ba970_0, C4<1>, C4<1>;
v00000154aa0ba830_0 .net *"_ivl_1", 0 0, L_00000154aa123f40; 1 drivers
v00000154aa0ba5b0_0 .net *"_ivl_3", 0 0, L_00000154aa0b3d30; 1 drivers
L_00000154aa130088 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v00000154aa0baa10_0 .net/2u *"_ivl_4", 0 0, L_00000154aa130088; 1 drivers
L_00000154aa1300d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000154aa0bad30_0 .net/2u *"_ivl_6", 0 0, L_00000154aa1300d0; 1 drivers
v00000154aa0ba150_0 .net "clk", 0 0, v00000154aa1235e0_0; 1 drivers
v00000154aa0ba1f0_0 .net "read_fifo", 0 0, v00000154aa124d00_0; 1 drivers
L_00000154aa130118 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000154aa0baf10_0 .net "rst", 0 0, L_00000154aa130118; 1 drivers
v00000154aa1244e0_0 .net "rx_data", 7 0, v00000154aa0c9f20_0; alias, 1 drivers
RS_00000154aa0ce488 .resolv tri, v00000154aa0c9200_0, v00000154aa124bc0_0;
v00000154aa123860_0 .net8 "rx_data_ready", 0 0, RS_00000154aa0ce488; 2 drivers
v00000154aa123540_0 .net "rx_data_valid", 0 0, o00000154aa0cf0e8; alias, 0 drivers
v00000154aa124300_0 .net "rx_fifo_empty", 0 0, v00000154aa0ca560_0; 1 drivers
v00000154aa123400_0 .net "rx_fifo_full", 0 0, v00000154aa0ca1a0_0; 1 drivers
v00000154aa123c20_0 .net "tx_data", 7 0, v00000154aa124b20_0; 1 drivers
v00000154aa123680_0 .net "tx_data_ready", 0 0, L_00000154aa123ea0; 1 drivers
v00000154aa124760_0 .net "tx_data_valid", 0 0, v00000154aa125200_0; 1 drivers
v00000154aa124c60_0 .net "tx_fifo_empty", 0 0, v00000154aa0ca100_0; 1 drivers
v00000154aa123b80_0 .net "tx_fifo_full", 0 0, v00000154aa0caec0_0; 1 drivers
v00000154aa1250c0_0 .net "uart_rx", 0 0, L_00000154aa0b4200; alias, 1 drivers
v00000154aa124a80_0 .net "uart_rx_data", 7 0, v00000154aa0ca600_0; 1 drivers
o00000154aa0ceba8 .functor BUFZ 1, c4<z>; HiZ drive
v00000154aa123e00_0 .net "uart_rx_data_ready", 0 0, o00000154aa0ceba8; 0 drivers
v00000154aa123900_0 .net "uart_rx_data_valid", 0 0, v00000154aa0c9700_0; 1 drivers
v00000154aa124260_0 .net "uart_tx", 0 0, v00000154aa0bac90_0; alias, 1 drivers
v00000154aa123cc0_0 .net "uart_tx_data", 7 0, v00000154aa0c9ca0_0; 1 drivers
v00000154aa124e40_0 .net "uart_tx_data_ready", 0 0, v00000154aa0ba970_0; 1 drivers
v00000154aa1239a0_0 .net "uart_tx_data_valid", 0 0, L_00000154aa123ae0; 1 drivers
L_00000154aa123f40 .reduce/nor v00000154aa0ca100_0;
L_00000154aa123ae0 .functor MUXZ 1, L_00000154aa1300d0, L_00000154aa130088, L_00000154aa0b3d30, C4<>;
S_00000154aa0a5580 .scope module, "rx_fifo_inst" "rx_fifo" 3 41, 4 1 0, S_00000154aa0a53f0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst_p";
.port_info 2 /INPUT 8 "rx_data_in";
.port_info 3 /INPUT 1 "rx_data_valid";
.port_info 4 /INPUT 1 "read_fifo";
.port_info 5 /OUTPUT 8 "rx_data_out";
.port_info 6 /OUTPUT 1 "rx_data_ready";
.port_info 7 /OUTPUT 1 "fifo_empty";
.port_info 8 /OUTPUT 1 "fifo_full";
P_00000154aa0b5de0 .param/l "DEPTH" 0 4 3, +C4<00000000000000000000000000010000>;
P_00000154aa0b5e18 .param/l "WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
v00000154aa0c93e0_0 .net "clk", 0 0, v00000154aa1235e0_0; alias, 1 drivers
v00000154aa0caa60_0 .var "fifo_count", 4 0;
v00000154aa0ca560_0 .var "fifo_empty", 0 0;
v00000154aa0ca1a0_0 .var "fifo_full", 0 0;
v00000154aa0c9c00 .array "fifo_mem", 0 15, 7 0;
v00000154aa0ca060_0 .var "rd_ptr", 4 0;
v00000154aa0ca7e0_0 .net "read_fifo", 0 0, v00000154aa124d00_0; alias, 1 drivers
v00000154aa0ca9c0_0 .net "rst_p", 0 0, L_00000154aa130118; alias, 1 drivers
v00000154aa0cab00_0 .net "rx_data_in", 7 0, v00000154aa0ca600_0; alias, 1 drivers
v00000154aa0c9f20_0 .var "rx_data_out", 7 0;
v00000154aa0c9200_0 .var "rx_data_ready", 0 0;
v00000154aa0cac40_0 .net "rx_data_valid", 0 0, v00000154aa0c9700_0; alias, 1 drivers
v00000154aa0ca880_0 .var "wr_ptr", 4 0;
E_00000154aa0c2b00 .event posedge, v00000154aa0ca9c0_0, v00000154aa0c93e0_0;
S_00000154aa0a5710 .scope module, "tx_fifo_inst" "tx_fifo" 3 57, 5 1 0, S_00000154aa0a53f0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst_p";
.port_info 2 /INPUT 8 "tx_data_in";
.port_info 3 /INPUT 1 "tx_data_valid";
.port_info 4 /OUTPUT 1 "tx_data_ready";
.port_info 5 /OUTPUT 8 "tx_data_out";
.port_info 6 /INPUT 1 "uart_tx_ready";
.port_info 7 /OUTPUT 1 "fifo_empty";
.port_info 8 /OUTPUT 1 "fifo_full";
P_00000154aa0b66e0 .param/l "DEPTH" 0 5 3, +C4<00000000000000000000000000010000>;
P_00000154aa0b6718 .param/l "WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
v00000154aa0caba0_0 .net "clk", 0 0, v00000154aa1235e0_0; alias, 1 drivers
v00000154aa0c92a0_0 .var "fifo_count", 4 0;
v00000154aa0ca100_0 .var "fifo_empty", 0 0;
v00000154aa0caec0_0 .var "fifo_full", 0 0;
v00000154aa0ca740 .array "fifo_mem", 0 15, 7 0;
v00000154aa0cae20_0 .var "rd_ptr", 4 0;
v00000154aa0c9e80_0 .net "rst_p", 0 0, L_00000154aa130118; alias, 1 drivers
v00000154aa0cad80_0 .net "tx_data_in", 7 0, v00000154aa124b20_0; alias, 1 drivers
v00000154aa0c9ca0_0 .var "tx_data_out", 7 0;
v00000154aa0c9480_0 .net "tx_data_ready", 0 0, L_00000154aa123ea0; alias, 1 drivers
v00000154aa0c9d40_0 .net "tx_data_valid", 0 0, v00000154aa125200_0; alias, 1 drivers
v00000154aa0caf60_0 .net "uart_tx_ready", 0 0, v00000154aa0ba970_0; alias, 1 drivers
v00000154aa0ca240_0 .var "wr_ptr", 4 0;
L_00000154aa123ea0 .reduce/nor v00000154aa0caec0_0;
S_00000154aa0952b0 .scope module, "uart_rx_inst" "uart_rx" 3 70, 6 1 0, S_00000154aa0a53f0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst_p";
.port_info 2 /INPUT 1 "rx_data_ready";
.port_info 3 /INPUT 1 "rx_pin";
.port_info 4 /OUTPUT 8 "rx_data";
.port_info 5 /OUTPUT 1 "rx_data_valid";
P_00000154aa095440 .param/l "BAUD_RATE" 0 6 3, +C4<00000000000000011100001000000000>;
P_00000154aa095478 .param/l "CLK_FREQ" 0 6 2, +C4<00000001100110111111110011000000>;
P_00000154aa0954b0 .param/l "CYCLE" 1 6 14, +C4<00000000000000000000000011101010>;
P_00000154aa0954e8 .param/l "S_DATA" 1 6 21, +C4<00000000000000000000000000000101>;
P_00000154aa095520 .param/l "S_IDLE" 1 6 17, +C4<00000000000000000000000000000001>;
P_00000154aa095558 .param/l "S_REC_BYTE" 1 6 19, +C4<00000000000000000000000000000011>;
P_00000154aa095590 .param/l "S_START" 1 6 18, +C4<00000000000000000000000000000010>;
P_00000154aa0955c8 .param/l "S_STOP" 1 6 20, +C4<00000000000000000000000000000100>;
L_00000154aa0b4740 .functor NOT 1, v00000154aa0ca420_0, C4<0>, C4<0>, C4<0>;
L_00000154aa0b4820 .functor AND 1, v00000154aa0ca4c0_0, L_00000154aa0b4740, C4<1>, C4<1>;
v00000154aa0ca2e0_0 .net *"_ivl_0", 0 0, L_00000154aa0b4740; 1 drivers
v00000154aa0c9a20_0 .var "bit_cnt", 2 0;
v00000154aa0c9340_0 .net "clk", 0 0, v00000154aa1235e0_0; alias, 1 drivers
v00000154aa0c9de0_0 .var "cycle_cnt", 15 0;
v00000154aa0c98e0_0 .var "next_state", 2 0;
v00000154aa0c95c0_0 .net "rst_p", 0 0, L_00000154aa130118; alias, 1 drivers
v00000154aa0c9980_0 .var "rx_bits", 7 0;
v00000154aa0ca420_0 .var "rx_d0", 0 0;
v00000154aa0ca4c0_0 .var "rx_d1", 0 0;
v00000154aa0ca600_0 .var "rx_data", 7 0;
v00000154aa0c9660_0 .net "rx_data_ready", 0 0, o00000154aa0ceba8; alias, 0 drivers
v00000154aa0c9700_0 .var "rx_data_valid", 0 0;
v00000154aa0c97a0_0 .net "rx_negedge", 0 0, L_00000154aa0b4820; 1 drivers
v00000154aa0c9ac0_0 .net "rx_pin", 0 0, L_00000154aa0b4200; alias, 1 drivers
v00000154aa0ba330_0 .var "state", 2 0;
E_00000154aa0c2980/0 .event anyedge, v00000154aa0ba330_0, v00000154aa0c97a0_0, v00000154aa0c9de0_0, v00000154aa0c9a20_0;
E_00000154aa0c2980/1 .event anyedge, v00000154aa0c9660_0;
E_00000154aa0c2980 .event/or E_00000154aa0c2980/0, E_00000154aa0c2980/1;
S_00000154aa08d130 .scope module, "uart_tx_inst" "uart_tx" 3 80, 7 1 0, S_00000154aa0a53f0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst_p";
.port_info 2 /INPUT 8 "data";
.port_info 3 /INPUT 1 "tx_data_valid";
.port_info 4 /OUTPUT 1 "tx";
.port_info 5 /OUTPUT 1 "tx_data_ready";
P_00000154aa08d2c0 .param/l "BAUD_RATE" 0 7 3, +C4<00000000000000011100001000000000>;
P_00000154aa08d2f8 .param/l "CLK_FREQ" 0 7 2, +C4<00000001100110111111110011000000>;
P_00000154aa08d330 .param/l "CYCLE" 1 7 14, +C4<00000000000000000000000011101010>;
P_00000154aa08d368 .param/l "DATA" 1 7 18, C4<10>;
P_00000154aa08d3a0 .param/l "IDLE" 1 7 16, C4<00>;
P_00000154aa08d3d8 .param/l "START" 1 7 17, C4<01>;
P_00000154aa08d410 .param/l "STOP" 1 7 19, C4<11>;
v00000154aa0ba290_0 .var "bit_cnt", 2 0;
v00000154aa0ba650_0 .net "clk", 0 0, v00000154aa1235e0_0; alias, 1 drivers
v00000154aa0ba6f0_0 .var "cycle_cnt", 15 0;
v00000154aa0baab0_0 .net "data", 7 0, v00000154aa0c9ca0_0; alias, 1 drivers
v00000154aa0bab50_0 .var "next_state", 1 0;
v00000154aa0ba0b0_0 .net "rst_p", 0 0, L_00000154aa130118; alias, 1 drivers
v00000154aa0ba790_0 .var "state", 1 0;
v00000154aa0ba3d0_0 .net "tx", 0 0, v00000154aa0bac90_0; alias, 1 drivers
v00000154aa0ba470_0 .var "tx_data_latch", 7 0;
v00000154aa0ba970_0 .var "tx_data_ready", 0 0;
v00000154aa0bae70_0 .net "tx_data_valid", 0 0, L_00000154aa123ae0; alias, 1 drivers
v00000154aa0bac90_0 .var "tx_reg", 0 0;
E_00000154aa0c26c0 .event anyedge, v00000154aa0ba790_0, v00000154aa0bae70_0, v00000154aa0ba6f0_0, v00000154aa0ba290_0;
.scope S_00000154aa0a5580;
T_0 ;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0ca880_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0ca060_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0caa60_0, 0, 5;
%end;
.thread T_0;
.scope S_00000154aa0a5580;
T_1 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ca9c0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0ca880_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0ca060_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0caa60_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0c9200_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0ca560_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0ca1a0_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v00000154aa0cac40_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_1.4, 9;
%load/vec4 v00000154aa0ca1a0_0;
%nor/r;
%and;
T_1.4;
%flag_set/vec4 8;
%jmp/0xz T_1.2, 8;
%load/vec4 v00000154aa0cab00_0;
%load/vec4 v00000154aa0ca880_0;
%pad/u 6;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v00000154aa0c9c00, 0, 4;
%load/vec4 v00000154aa0ca880_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0ca880_0, 0;
%load/vec4 v00000154aa0caa60_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0caa60_0, 0;
T_1.2 ;
%load/vec4 v00000154aa0ca560_0;
%nor/r;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_1.7, 9;
%load/vec4 v00000154aa0ca7e0_0;
%and;
T_1.7;
%flag_set/vec4 8;
%jmp/0xz T_1.5, 8;
%load/vec4 v00000154aa0ca060_0;
%pad/u 6;
%ix/vec4 4;
%load/vec4a v00000154aa0c9c00, 4;
%assign/vec4 v00000154aa0c9f20_0, 0;
%load/vec4 v00000154aa0ca060_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0ca060_0, 0;
%load/vec4 v00000154aa0caa60_0;
%subi 1, 0, 5;
%assign/vec4 v00000154aa0caa60_0, 0;
T_1.5 ;
%load/vec4 v00000154aa0caa60_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%assign/vec4 v00000154aa0ca560_0, 0;
%load/vec4 v00000154aa0caa60_0;
%pad/u 32;
%pushi/vec4 16, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%assign/vec4 v00000154aa0ca1a0_0, 0;
%load/vec4 v00000154aa0ca560_0;
%nor/r;
%assign/vec4 v00000154aa0c9200_0, 0;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_00000154aa0a5710;
T_2 ;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0ca240_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0cae20_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v00000154aa0c92a0_0, 0, 5;
%end;
.thread T_2;
.scope S_00000154aa0a5710;
T_3 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0cae20_0;
%pad/u 6;
%ix/vec4 4;
%load/vec4a v00000154aa0ca740, 4;
%assign/vec4 v00000154aa0c9ca0_0, 0;
%load/vec4 v00000154aa0c9e80_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0ca240_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0cae20_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v00000154aa0c92a0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0ca100_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0caec0_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v00000154aa0c9ca0_0, 0;
%jmp T_3.1;
T_3.0 ;
%load/vec4 v00000154aa0c9d40_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_3.4, 9;
%load/vec4 v00000154aa0caec0_0;
%nor/r;
%and;
T_3.4;
%flag_set/vec4 8;
%jmp/0xz T_3.2, 8;
%load/vec4 v00000154aa0cad80_0;
%load/vec4 v00000154aa0ca240_0;
%pad/u 6;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v00000154aa0ca740, 0, 4;
%load/vec4 v00000154aa0ca240_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0ca240_0, 0;
%load/vec4 v00000154aa0c92a0_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0c92a0_0, 0;
T_3.2 ;
%load/vec4 v00000154aa0caf60_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_3.7, 9;
%load/vec4 v00000154aa0ca100_0;
%nor/r;
%and;
T_3.7;
%flag_set/vec4 8;
%jmp/0xz T_3.5, 8;
%load/vec4 v00000154aa0cae20_0;
%addi 1, 0, 5;
%assign/vec4 v00000154aa0cae20_0, 0;
%load/vec4 v00000154aa0c92a0_0;
%subi 1, 0, 5;
%assign/vec4 v00000154aa0c92a0_0, 0;
T_3.5 ;
%load/vec4 v00000154aa0c92a0_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%assign/vec4 v00000154aa0ca100_0, 0;
%load/vec4 v00000154aa0c92a0_0;
%pad/u 32;
%pushi/vec4 16, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%assign/vec4 v00000154aa0caec0_0, 0;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_00000154aa0952b0;
T_4 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_4.0, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0ca420_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0ca4c0_0, 0;
%jmp T_4.1;
T_4.0 ;
%load/vec4 v00000154aa0c9ac0_0;
%assign/vec4 v00000154aa0ca420_0, 0;
%load/vec4 v00000154aa0ca420_0;
%assign/vec4 v00000154aa0ca4c0_0, 0;
T_4.1 ;
%jmp T_4;
.thread T_4;
.scope S_00000154aa0952b0;
T_5 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_5.0, 4;
%pushi/vec4 1, 0, 3;
%assign/vec4 v00000154aa0ba330_0, 0;
%jmp T_5.1;
T_5.0 ;
%load/vec4 v00000154aa0c98e0_0;
%assign/vec4 v00000154aa0ba330_0, 0;
T_5.1 ;
%jmp T_5;
.thread T_5;
.scope S_00000154aa0952b0;
T_6 ;
%wait E_00000154aa0c2980;
%load/vec4 v00000154aa0ba330_0;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_6.0, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_6.1, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_6.2, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_6.3, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_6.4, 6;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.6;
T_6.0 ;
%load/vec4 v00000154aa0c97a0_0;
%flag_set/vec4 8;
%jmp/0xz T_6.7, 8;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.8;
T_6.7 ;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
T_6.8 ;
%jmp T_6.6;
T_6.1 ;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%jmp/0xz T_6.9, 4;
%pushi/vec4 3, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.10;
T_6.9 ;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
T_6.10 ;
%jmp T_6.6;
T_6.2 ;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_6.13, 4;
%load/vec4 v00000154aa0c9a20_0;
%pushi/vec4 7, 0, 3;
%cmp/e;
%flag_get/vec4 4;
%and;
T_6.13;
%flag_set/vec4 8;
%jmp/0xz T_6.11, 8;
%pushi/vec4 4, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.12;
T_6.11 ;
%pushi/vec4 3, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
T_6.12 ;
%jmp T_6.6;
T_6.3 ;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%cmpi/e 116, 0, 32;
%jmp/0xz T_6.14, 4;
%pushi/vec4 5, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.15;
T_6.14 ;
%pushi/vec4 4, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
T_6.15 ;
%jmp T_6.6;
T_6.4 ;
%load/vec4 v00000154aa0c9660_0;
%flag_set/vec4 8;
%jmp/0xz T_6.16, 8;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
%jmp T_6.17;
T_6.16 ;
%pushi/vec4 5, 0, 3;
%store/vec4 v00000154aa0c98e0_0, 0, 3;
T_6.17 ;
%jmp T_6.6;
T_6.6 ;
%pop/vec4 1;
%jmp T_6;
.thread T_6, $push;
.scope S_00000154aa0952b0;
T_7 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_7.0, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0c9700_0, 0;
%jmp T_7.1;
T_7.0 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 4, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_7.4, 4;
%load/vec4 v00000154aa0c98e0_0;
%load/vec4 v00000154aa0ba330_0;
%cmp/ne;
%flag_get/vec4 4;
%and;
T_7.4;
%flag_set/vec4 8;
%jmp/0xz T_7.2, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0c9700_0, 0;
%jmp T_7.3;
T_7.2 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 5, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_7.7, 4;
%load/vec4 v00000154aa0c9660_0;
%and;
T_7.7;
%flag_set/vec4 8;
%jmp/0xz T_7.5, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0c9700_0, 0;
T_7.5 ;
T_7.3 ;
T_7.1 ;
%jmp T_7;
.thread T_7;
.scope S_00000154aa0952b0;
T_8 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_8.0, 4;
%pushi/vec4 0, 0, 8;
%assign/vec4 v00000154aa0ca600_0, 0;
%jmp T_8.1;
T_8.0 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 4, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_8.4, 4;
%load/vec4 v00000154aa0c98e0_0;
%load/vec4 v00000154aa0ba330_0;
%cmp/ne;
%flag_get/vec4 4;
%and;
T_8.4;
%flag_set/vec4 8;
%jmp/0xz T_8.2, 8;
%load/vec4 v00000154aa0c9980_0;
%assign/vec4 v00000154aa0ca600_0, 0;
T_8.2 ;
T_8.1 ;
%jmp T_8;
.thread T_8;
.scope S_00000154aa0952b0;
T_9 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_9.0, 4;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000154aa0c9a20_0, 0;
%jmp T_9.1;
T_9.0 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 3, 0, 32;
%jmp/0xz T_9.2, 4;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%jmp/0xz T_9.4, 4;
%load/vec4 v00000154aa0c9a20_0;
%addi 1, 0, 3;
%assign/vec4 v00000154aa0c9a20_0, 0;
%jmp T_9.5;
T_9.4 ;
%load/vec4 v00000154aa0c9a20_0;
%assign/vec4 v00000154aa0c9a20_0, 0;
T_9.5 ;
%jmp T_9.3;
T_9.2 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000154aa0c9a20_0, 0;
T_9.3 ;
T_9.1 ;
%jmp T_9;
.thread T_9;
.scope S_00000154aa0952b0;
T_10 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_10.0, 4;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000154aa0c9de0_0, 0;
%jmp T_10.1;
T_10.0 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 3, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_10.5, 4;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%pushi/vec4 233, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
T_10.5;
%flag_set/vec4 8;
%jmp/1 T_10.4, 8;
%load/vec4 v00000154aa0c98e0_0;
%load/vec4 v00000154aa0ba330_0;
%cmp/ne;
%flag_or 8, 4;
T_10.4;
%jmp/0xz T_10.2, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000154aa0c9de0_0, 0;
%jmp T_10.3;
T_10.2 ;
%load/vec4 v00000154aa0c9de0_0;
%addi 1, 0, 16;
%assign/vec4 v00000154aa0c9de0_0, 0;
T_10.3 ;
T_10.1 ;
%jmp T_10;
.thread T_10;
.scope S_00000154aa0952b0;
T_11 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0c95c0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_11.0, 4;
%pushi/vec4 0, 0, 8;
%assign/vec4 v00000154aa0c9980_0, 0;
%jmp T_11.1;
T_11.0 ;
%load/vec4 v00000154aa0ba330_0;
%pad/u 32;
%cmpi/e 3, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_11.4, 4;
%load/vec4 v00000154aa0c9de0_0;
%pad/u 32;
%pushi/vec4 116, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
T_11.4;
%flag_set/vec4 8;
%jmp/0xz T_11.2, 8;
%load/vec4 v00000154aa0c9ac0_0;
%ix/load 5, 0, 0;
%ix/getv 4, v00000154aa0c9a20_0;
%assign/vec4/off/d v00000154aa0c9980_0, 4, 5;
%jmp T_11.3;
T_11.2 ;
%load/vec4 v00000154aa0c9980_0;
%assign/vec4 v00000154aa0c9980_0, 0;
T_11.3 ;
T_11.1 ;
%jmp T_11;
.thread T_11;
.scope S_00000154aa08d130;
T_12 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000154aa0ba790_0, 0, 2;
%pushi/vec4 0, 0, 8;
%store/vec4 v00000154aa0ba470_0, 0, 8;
%end;
.thread T_12;
.scope S_00000154aa08d130;
T_13 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_13.0, 4;
%pushi/vec4 0, 0, 2;
%assign/vec4 v00000154aa0ba790_0, 0;
%jmp T_13.1;
T_13.0 ;
%load/vec4 v00000154aa0bab50_0;
%assign/vec4 v00000154aa0ba790_0, 0;
T_13.1 ;
%jmp T_13;
.thread T_13;
.scope S_00000154aa08d130;
T_14 ;
%wait E_00000154aa0c26c0;
%load/vec4 v00000154aa0ba790_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_14.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_14.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_14.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_14.3, 6;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
%jmp T_14.5;
T_14.0 ;
%load/vec4 v00000154aa0bae70_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_14.6, 4;
%pushi/vec4 1, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
%jmp T_14.7;
T_14.6 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
T_14.7 ;
%jmp T_14.5;
T_14.1 ;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%jmp/0xz T_14.8, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
%jmp T_14.9;
T_14.8 ;
%pushi/vec4 1, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
T_14.9 ;
%jmp T_14.5;
T_14.2 ;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%flag_get/vec4 4;
%jmp/0 T_14.12, 4;
%load/vec4 v00000154aa0ba290_0;
%pushi/vec4 7, 0, 3;
%cmp/e;
%flag_get/vec4 4;
%and;
T_14.12;
%flag_set/vec4 8;
%jmp/0xz T_14.10, 8;
%pushi/vec4 3, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
%jmp T_14.11;
T_14.10 ;
%pushi/vec4 2, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
T_14.11 ;
%jmp T_14.5;
T_14.3 ;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%jmp/0xz T_14.13, 4;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
%jmp T_14.14;
T_14.13 ;
%pushi/vec4 3, 0, 2;
%store/vec4 v00000154aa0bab50_0, 0, 2;
T_14.14 ;
%jmp T_14.5;
T_14.5 ;
%pop/vec4 1;
%jmp T_14;
.thread T_14, $push;
.scope S_00000154aa08d130;
T_15 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_15.0, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0ba970_0, 0;
%jmp T_15.1;
T_15.0 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 0, 0, 2;
%flag_get/vec4 4;
%jmp/0 T_15.4, 4;
%load/vec4 v00000154aa0bae70_0;
%pushi/vec4 1, 0, 1;
%cmp/e;
%flag_get/vec4 4;
%and;
T_15.4;
%flag_set/vec4 8;
%jmp/0xz T_15.2, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0ba970_0, 0;
%jmp T_15.3;
T_15.2 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 0, 0, 2;
%jmp/0xz T_15.5, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0ba970_0, 0;
%jmp T_15.6;
T_15.5 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 3, 0, 2;
%flag_get/vec4 4;
%jmp/0 T_15.9, 4;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%pushi/vec4 233, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
T_15.9;
%flag_set/vec4 8;
%jmp/0xz T_15.7, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0ba970_0, 0;
%jmp T_15.8;
T_15.7 ;
%load/vec4 v00000154aa0ba970_0;
%assign/vec4 v00000154aa0ba970_0, 0;
T_15.8 ;
T_15.6 ;
T_15.3 ;
T_15.1 ;
%jmp T_15;
.thread T_15;
.scope S_00000154aa08d130;
T_16 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_16.0, 4;
%pushi/vec4 0, 0, 8;
%assign/vec4 v00000154aa0ba470_0, 0;
%jmp T_16.1;
T_16.0 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 0, 0, 2;
%flag_get/vec4 4;
%jmp/0 T_16.4, 4;
%load/vec4 v00000154aa0bae70_0;
%pushi/vec4 1, 0, 1;
%cmp/e;
%flag_get/vec4 4;
%and;
T_16.4;
%flag_set/vec4 8;
%jmp/0xz T_16.2, 8;
%load/vec4 v00000154aa0baab0_0;
%assign/vec4 v00000154aa0ba470_0, 0;
T_16.2 ;
T_16.1 ;
%jmp T_16;
.thread T_16;
.scope S_00000154aa08d130;
T_17 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_17.0, 4;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000154aa0ba290_0, 0;
%jmp T_17.1;
T_17.0 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 2, 0, 2;
%jmp/0xz T_17.2, 4;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%cmpi/e 233, 0, 32;
%jmp/0xz T_17.4, 4;
%load/vec4 v00000154aa0ba290_0;
%addi 1, 0, 3;
%assign/vec4 v00000154aa0ba290_0, 0;
%jmp T_17.5;
T_17.4 ;
%load/vec4 v00000154aa0ba290_0;
%assign/vec4 v00000154aa0ba290_0, 0;
T_17.5 ;
%jmp T_17.3;
T_17.2 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000154aa0ba290_0, 0;
T_17.3 ;
T_17.1 ;
%jmp T_17;
.thread T_17;
.scope S_00000154aa08d130;
T_18 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_18.0, 4;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000154aa0ba6f0_0, 0;
%jmp T_18.1;
T_18.0 ;
%load/vec4 v00000154aa0ba790_0;
%cmpi/e 2, 0, 2;
%flag_get/vec4 4;
%jmp/0 T_18.5, 4;
%load/vec4 v00000154aa0ba6f0_0;
%pad/u 32;
%pushi/vec4 233, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
T_18.5;
%flag_set/vec4 8;
%jmp/1 T_18.4, 8;
%load/vec4 v00000154aa0bab50_0;
%load/vec4 v00000154aa0ba790_0;
%cmp/ne;
%flag_or 8, 4;
T_18.4;
%jmp/0xz T_18.2, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000154aa0ba6f0_0, 0;
%jmp T_18.3;
T_18.2 ;
%load/vec4 v00000154aa0ba6f0_0;
%addi 1, 0, 16;
%assign/vec4 v00000154aa0ba6f0_0, 0;
T_18.3 ;
T_18.1 ;
%jmp T_18;
.thread T_18;
.scope S_00000154aa08d130;
T_19 ;
%wait E_00000154aa0c2b00;
%load/vec4 v00000154aa0ba0b0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_19.0, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.1;
T_19.0 ;
%load/vec4 v00000154aa0ba790_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_19.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_19.3, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_19.4, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_19.5, 6;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.7;
T_19.2 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.7;
T_19.3 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.7;
T_19.4 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.7;
T_19.5 ;
%load/vec4 v00000154aa0ba470_0;
%load/vec4 v00000154aa0ba290_0;
%part/u 1;
%assign/vec4 v00000154aa0bac90_0, 0;
%jmp T_19.7;
T_19.7 ;
%pop/vec4 1;
T_19.1 ;
%jmp T_19;
.thread T_19;
.scope S_00000154aa078310;
T_20 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000154aa1235e0_0, 0, 1;
%pushi/vec4 0, 0, 8;
%store/vec4 v00000154aa124b20_0, 0, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000154aa124d00_0, 0, 1;
%end;
.thread T_20;
.scope S_00000154aa078310;
T_21 ;
%delay 18500, 0;
%load/vec4 v00000154aa1235e0_0;
%inv;
%store/vec4 v00000154aa1235e0_0, 0, 1;
%jmp T_21;
.thread T_21;
.scope S_00000154aa078310;
T_22 ;
%vpi_call 2 39 "$display", "Debut de la simulation" {0 0 0};
%vpi_call 2 40 "$dumpfile", "uart_loopback.vcd" {0 0 0};
%vpi_call 2 41 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000154aa078310 {0 0 0};
%delay 200000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000154aa124bc0_0, 0, 1;
%pushi/vec4 165, 0, 8;
%store/vec4 v00000154aa124b20_0, 0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000154aa125200_0, 0, 1;
%delay 20000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000154aa125200_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000154aa124bc0_0, 0, 1;
%delay 200000, 0;
%vpi_call 2 58 "$display", "Attente de rx_data_valid" {0 0 0};
T_22.0 ;
%load/vec4 v00000154aa124580_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_22.1, 6;
%wait E_00000154aa0c27c0;
%jmp T_22.0;
T_22.1 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000154aa124d00_0, 0, 1;
%vpi_call 2 64 "$display", "Data envoyee : 0x%h", v00000154aa124b20_0 {0 0 0};
%vpi_call 2 65 "$display", "Data recue : 0x%h", v00000154aa123720_0 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v00000154aa124d00_0, 0, 1;
%load/vec4 v00000154aa123720_0;
%load/vec4 v00000154aa124b20_0;
%cmp/e;
%jmp/0xz T_22.2, 4;
%vpi_call 2 70 "$display", "Test reussi !" {0 0 0};
%jmp T_22.3;
T_22.2 ;
%vpi_call 2 72 "$display", "Test echoue..." {0 0 0};
T_22.3 ;
%delay 200000, 0;
%vpi_call 2 76 "$finish" {0 0 0};
%end;
.thread T_22;
# The file index is used to find the file name in the following table.
:file_names 8;
"N/A";
"<interactive>";
"tb_top_uart_rx_tx.v";
"uart_top.v";
"rx_fifo.v";
"tx_fifo.v";
"uart_rx.v";
"uart_tx.v";
Copy Permalink