forked from tanchou/Verilog
473 lines
14 KiB
Coq
473 lines
14 KiB
Coq
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: txuartlite.v
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// {{{
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// Project: wbuart32, a full featured UART with simulator
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//
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// Purpose: Transmit outputs over a single UART line. This particular UART
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// implementation has been extremely simplified: it does not handle
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// generating break conditions, nor does it handle anything other than the
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// 8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol.
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//
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// To interface with this module, connect it to your system clock, and
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// pass it the byte of data you wish to transmit. Strobe the i_wr line
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// high for one cycle, and your data will be off. Wait until the 'o_busy'
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// line is low before strobing the i_wr line again--this implementation
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// has NO BUFFER, so strobing i_wr while the core is busy will just
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// get ignored. The output will be placed on the o_txuart output line.
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//
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// (I often set both data and strobe on the same clock, and then just leave
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// them set until the busy line is low. Then I move on to the next piece
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// of data.)
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2015-2024, Gisselquist Technology, LLC
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// {{{
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// }}}
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// License: GPL, v3, as defined and found on www.gnu.org,
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// {{{
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// http://www.gnu.org/licenses/gpl.html
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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`default_nettype none
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// }}}
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module txuartlite #(
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// {{{
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// TIMING_BITS -- the number of bits required to represent
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// the number of clocks per baud. 24 should be sufficient for
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// most baud rates, but you can trim it down to save logic if
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// you would like. TB is just an abbreviation for TIMING_BITS.
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parameter [4:0] TIMING_BITS = 5'd8,
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localparam TB = TIMING_BITS,
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// CLOCKS_PER_BAUD -- the number of system clocks per baud
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// interval.
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parameter [(TB-1):0] CLOCKS_PER_BAUD = 234 // 24'd868
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// }}}
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) (
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// {{{
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input wire i_clk, i_reset,
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input wire i_wr,
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input wire [7:0] i_data,
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// And the UART input line itself
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output reg o_uart_tx,
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// A line to tell others when we are ready to accept data. If
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted
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// a byte for transmission.
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output wire o_busy
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// }}}
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);
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// Register/net declarations
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// {{{
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localparam [3:0] TXUL_BIT_ZERO = 4'h0,
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// TXUL_BIT_ONE = 4'h1,
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// TXUL_BIT_TWO = 4'h2,
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// TXUL_BIT_THREE = 4'h3,
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// TXUL_BIT_FOUR = 4'h4,
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// TXUL_BIT_FIVE = 4'h5,
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// TXUL_BIT_SIX = 4'h6,
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// TXUL_BIT_SEVEN = 4'h7,
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TXUL_STOP = 4'h8,
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TXUL_IDLE = 4'hf;
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reg [(TB-1):0] baud_counter;
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reg [3:0] state;
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reg [7:0] lcl_data;
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reg r_busy, zero_baud_counter;
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// }}}
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// Big state machine controlling: r_busy, state
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// {{{
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//
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initial r_busy = 1'b1;
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initial state = TXUL_IDLE;
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always @(posedge i_clk)
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if (i_reset)
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begin
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r_busy <= 1'b1;
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state <= TXUL_IDLE;
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end else if (!zero_baud_counter)
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// r_busy needs to be set coming into here
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r_busy <= 1'b1;
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else if (state > TXUL_STOP) // STATE_IDLE
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begin
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state <= TXUL_IDLE;
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r_busy <= 1'b0;
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if ((i_wr)&&(!r_busy))
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begin // Immediately start us off with a start bit
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r_busy <= 1'b1;
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state <= TXUL_BIT_ZERO;
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end
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end else begin
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// One clock tick in each of these states ...
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r_busy <= 1'b1;
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if (state <=TXUL_STOP) // start bit, 8-d bits, stop-b
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state <= state + 1'b1;
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else
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state <= TXUL_IDLE;
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end
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// }}}
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// o_busy
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// {{{
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//
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// This is a wire, designed to be true is we are ever busy above.
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// originally, this was going to be true if we were ever not in the
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// idle state. The logic has since become more complex, hence we have
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// a register dedicated to this and just copy out that registers value.
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assign o_busy = (r_busy);
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// }}}
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// lcl_data
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// {{{
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//
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// This is our working copy of the i_data register which we use
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// when transmitting. It is only of interest during transmit, and is
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// allowed to be whatever at any other time. Hence, if r_busy isn't
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// true, we can always set it. On the one clock where r_busy isn't
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// true and i_wr is, we set it and r_busy is true thereafter.
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// Then, on any zero_baud_counter (i.e. change between baud intervals)
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// we simple logically shift the register right to grab the next bit.
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initial lcl_data = 8'hff;
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always @(posedge i_clk)
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if (i_reset)
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lcl_data <= 8'hff;
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else if (i_wr && !r_busy)
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lcl_data <= i_data;
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else if (zero_baud_counter)
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lcl_data <= { 1'b1, lcl_data[7:1] };
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// }}}
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// o_uart_tx
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// {{{
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//
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// This is the final result/output desired of this core. It's all
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// centered about o_uart_tx. This is what finally needs to follow
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// the UART protocol.
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//
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initial o_uart_tx = 1'b1;
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always @(posedge i_clk)
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if (i_reset)
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o_uart_tx <= 1'b1;
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else if (i_wr && !r_busy)
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o_uart_tx <= 1'b0; // Set the start bit on writes
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else if (zero_baud_counter) // Set the data bit.
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o_uart_tx <= lcl_data[0];
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// }}}
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// Baud counter
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// {{{
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// All of the above logic is driven by the baud counter. Bits must last
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// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
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// make certain of that.
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//
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// The basic logic is this: at the beginning of a bit interval, start
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// the baud counter and set it to count CLOCKS_PER_BAUD. When it gets
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// to zero, restart it.
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//
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// However, comparing a 28'bit number to zero can be rather complex--
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// especially if we wish to do anything else on that same clock. For
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// that reason, we create "zero_baud_counter". zero_baud_counter is
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// nothing more than a flag that is true anytime baud_counter is zero.
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// It's true when the logic (above) needs to step to the next bit.
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// Simple enough?
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//
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// I wish we could stop there, but there are some other (ugly)
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// conditions to deal with that offer exceptions to this basic logic.
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//
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// 1. When the user has commanded a BREAK across the line, we need to
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// wait several baud intervals following the break before we start
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// transmitting, to give any receiver a chance to recognize that we are
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// out of the break condition, and to know that the next bit will be
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// a stop bit.
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//
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// 2. A reset is similar to a break condition--on both we wait several
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// baud intervals before allowing a start bit.
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//
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// 3. In the idle state, we stop our counter--so that upon a request
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// to transmit when idle we can start transmitting immediately, rather
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// than waiting for the end of the next (fictitious and arbitrary) baud
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// interval.
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//
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// When (i_wr)&&(!r_busy)&&(state == TXUL_IDLE) then we're not only in
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// the idle state, but we also just accepted a command to start writing
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// the next word. At this point, the baud counter needs to be reset
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// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
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//
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// The logic is a bit twisted here, in that it will only check for the
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// above condition when zero_baud_counter is false--so as to make
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// certain the STOP bit is complete.
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initial zero_baud_counter = 1'b1;
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initial baud_counter = 0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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zero_baud_counter <= 1'b1;
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baud_counter <= 0;
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end else begin
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zero_baud_counter <= (baud_counter == 1);
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if (state == TXUL_IDLE)
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begin
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baud_counter <= 0;
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zero_baud_counter <= 1'b1;
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if ((i_wr)&&(!r_busy))
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begin
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baud_counter <= CLOCKS_PER_BAUD - 1'b1;
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zero_baud_counter <= 1'b0;
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end
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end else if (!zero_baud_counter)
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baud_counter <= baud_counter - 1'b1;
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else if (state > TXUL_STOP)
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begin
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baud_counter <= 0;
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zero_baud_counter <= 1'b1;
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end else if (state == TXUL_STOP)
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// Need to complete this state one clock early, so
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// we can release busy one clock before the stop bit
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// is complete, so we can start on the next byte
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// exactly 10*CLOCKS_PER_BAUD clocks after we started
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// the last one
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baud_counter <= CLOCKS_PER_BAUD - 2;
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else // All other states
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baud_counter <= CLOCKS_PER_BAUD - 1'b1;
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end
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// }}}
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// FORMAL METHODS
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// {{{
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`ifdef FORMAL
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// Declarations
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`ifdef TXUARTLITE
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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reg f_past_valid, f_last_clk;
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reg [(TB-1):0] f_baud_count;
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reg [9:0] f_txbits;
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reg [3:0] f_bitcount;
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reg [7:0] f_request_tx_data;
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wire [3:0] subcount;
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// Setup
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// {{{
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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initial `ASSUME(!i_wr);
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_wr))&&($past(o_busy)))
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begin
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`ASSUME(i_wr == $past(i_wr));
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`ASSUME(i_data == $past(i_data));
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end
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// }}}
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// Check the baud counter
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// {{{
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always @(posedge i_clk)
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assert(zero_baud_counter == (baud_counter == 0));
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always @(posedge i_clk)
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if (f_past_valid && !$past(i_reset) && $past(baud_counter != 0)
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&& $past(state != TXUL_IDLE))
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assert(baud_counter == $past(baud_counter - 1'b1));
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always @(posedge i_clk)
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if (f_past_valid && !$past(i_reset) && !$past(zero_baud_counter)
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&& $past(state != TXUL_IDLE))
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assert($stable(o_uart_tx));
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initial f_baud_count = 1'b0;
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always @(posedge i_clk)
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if (zero_baud_counter)
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f_baud_count <= 0;
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else
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f_baud_count <= f_baud_count + 1'b1;
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always @(posedge i_clk)
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assert(f_baud_count < CLOCKS_PER_BAUD);
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always @(posedge i_clk)
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if (baud_counter != 0)
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assert(o_busy);
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// }}}
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// {{{
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initial f_txbits = 0;
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always @(posedge i_clk)
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if (zero_baud_counter)
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f_txbits <= { o_uart_tx, f_txbits[9:1] };
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always @(posedge i_clk)
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if (f_past_valid && !$past(i_reset)&& !$past(zero_baud_counter)
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&& !$past(state==TXUL_IDLE))
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assert(state == $past(state));
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initial f_bitcount = 0;
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always @(posedge i_clk)
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if ((!f_past_valid)||(!$past(f_past_valid)))
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f_bitcount <= 0;
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else if ((state == TXUL_IDLE)&&(zero_baud_counter))
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f_bitcount <= 0;
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else if (zero_baud_counter)
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f_bitcount <= f_bitcount + 1'b1;
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always @(posedge i_clk)
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assert(f_bitcount <= 4'ha);
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always @(*)
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if (!o_busy)
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assert(zero_baud_counter);
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always @(posedge i_clk)
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if ((i_wr)&&(!o_busy))
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f_request_tx_data <= i_data;
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||
|
|
|
||
|
|
assign subcount = 10-f_bitcount;
|
||
|
|
always @(posedge i_clk)
|
||
|
|
if (f_bitcount > 0)
|
||
|
|
assert(!f_txbits[subcount]);
|
||
|
|
|
||
|
|
always @(posedge i_clk)
|
||
|
|
if (f_bitcount == 4'ha)
|
||
|
|
begin
|
||
|
|
assert(f_txbits[8:1] == f_request_tx_data);
|
||
|
|
assert( f_txbits[9]);
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge i_clk)
|
||
|
|
assert((state <= TXUL_STOP + 1'b1)||(state == TXUL_IDLE));
|
||
|
|
|
||
|
|
always @(posedge i_clk)
|
||
|
|
if ((f_past_valid)&&($past(f_past_valid))&&($past(o_busy)))
|
||
|
|
cover(!o_busy);
|
||
|
|
// }}}
|
||
|
|
|
||
|
|
`endif // FORMAL
|
||
|
|
`ifdef VERIFIC_SVA
|
||
|
|
reg [7:0] fsv_data;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Grab a copy of the data any time we are sent a new byte to transmit
|
||
|
|
// We'll use this in a moment to compare the item transmitted against
|
||
|
|
// what is supposed to be transmitted
|
||
|
|
//
|
||
|
|
always @(posedge i_clk)
|
||
|
|
if ((i_wr)&&(!o_busy))
|
||
|
|
fsv_data <= i_data;
|
||
|
|
|
||
|
|
//
|
||
|
|
// One baud interval
|
||
|
|
// {{{
|
||
|
|
//
|
||
|
|
// 1. The UART output is constant at DAT
|
||
|
|
// 2. The internal state remains constant at ST
|
||
|
|
// 3. CKS = the number of clocks per bit.
|
||
|
|
//
|
||
|
|
// Everything stays constant during the CKS clocks with the exception
|
||
|
|
// of (zero_baud_counter), which is *only* raised on the last clock
|
||
|
|
// interval
|
||
|
|
sequence BAUD_INTERVAL(CKS, DAT, SR, ST);
|
||
|
|
((o_uart_tx == DAT)&&(state == ST)
|
||
|
|
&&(lcl_data == SR)
|
||
|
|
&&(!zero_baud_counter))[*(CKS-1)]
|
||
|
|
##1 (o_uart_tx == DAT)&&(state == ST)
|
||
|
|
&&(lcl_data == SR)
|
||
|
|
&&(zero_baud_counter);
|
||
|
|
endsequence
|
||
|
|
// }}}
|
||
|
|
|
||
|
|
//
|
||
|
|
// One byte transmitted
|
||
|
|
// {{{
|
||
|
|
//
|
||
|
|
// DATA = the byte that is sent
|
||
|
|
// CKS = the number of clocks per bit
|
||
|
|
//
|
||
|
|
sequence SEND(CKS, DATA);
|
||
|
|
BAUD_INTERVAL(CKS, 1'b0, DATA, 4'h0)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h1)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h2)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h3)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h4)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h5)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[5], {{(6){1'b1}},DATA[7:6]}, 4'h6)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[6], {{(7){1'b1}},DATA[7:7]}, 4'h7)
|
||
|
|
##1 BAUD_INTERVAL(CKS, DATA[7], 8'hff, 4'h8)
|
||
|
|
##1 BAUD_INTERVAL(CKS-1, 1'b1, 8'hff, 4'h9);
|
||
|
|
endsequence
|
||
|
|
// }}}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Transmit one byte
|
||
|
|
// {{{
|
||
|
|
// Once the byte is transmitted, make certain we return to
|
||
|
|
// idle
|
||
|
|
//
|
||
|
|
assert property (
|
||
|
|
@(posedge i_clk)
|
||
|
|
(i_wr)&&(!o_busy)
|
||
|
|
|=> ((o_busy) throughout SEND(CLOCKS_PER_BAUD,fsv_data))
|
||
|
|
##1 (!o_busy)&&(o_uart_tx)&&(zero_baud_counter));
|
||
|
|
// }}}
|
||
|
|
|
||
|
|
// {{{
|
||
|
|
assume property (
|
||
|
|
@(posedge i_clk)
|
||
|
|
(i_wr)&&(o_busy) |=>
|
||
|
|
(i_wr)&&($stable(i_data)));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Make certain that o_busy is true any time zero_baud_counter is
|
||
|
|
// non-zero
|
||
|
|
//
|
||
|
|
always @(*)
|
||
|
|
assert((o_busy)||(zero_baud_counter) );
|
||
|
|
|
||
|
|
// If and only if zero_baud_counter is true, baud_counter must be zero
|
||
|
|
// Insist on that relationship here.
|
||
|
|
always @(*)
|
||
|
|
assert(zero_baud_counter == (baud_counter == 0));
|
||
|
|
|
||
|
|
// To make certain baud_counter stays below CLOCKS_PER_BAUD
|
||
|
|
always @(*)
|
||
|
|
assert(baud_counter < CLOCKS_PER_BAUD);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Insist that we are only ever in a valid state
|
||
|
|
always @(*)
|
||
|
|
assert((state <= TXUL_STOP+1'b1)||(state == TXUL_IDLE));
|
||
|
|
// }}}
|
||
|
|
|
||
|
|
`endif // Verific SVA
|
||
|
|
// }}}
|
||
|
|
endmodule
|