forked from tanchou/Verilog
36 lines
1.0 KiB
Coq
36 lines
1.0 KiB
Coq
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module dht11_interface (
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input wire i_clk, // 27 MHz
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inout wire io_dht11_sig,
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output wire o_dht11_data_ready,
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output wire [7:0] o_temp_data,
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output wire [7:0] o_hum_data,
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output wire o_dht11_error
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);
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// === DHT11 INTERFACE ===
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// Le module DHT11 est connecté à la broche io_dht11_sig.
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// La communication se fait en mode bidirectionnel.
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wire sig_dir;
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wire sig_out;
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assign io_dht11_sig = sig_dir ? sig_out : 1'bz;
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// === FSM ===
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localparam IDLE = 3'd0, // Pull up la ligne
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START = 3'd1, // Pull low 18ms
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WAIT_RESPONSE = 3'd2, // Release la ligne (entre 20 et 40us)
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READ_HUM_INT = 3'd3,
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READ_HUM_DEC = 3'd4;
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READ_TEMP_INT = 3'd5,
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READ_TEMP_DEC = 3'd6,
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READ_CHECKSUM = 3'd7, // Last 8 bits of {1st Byte + 2nd Byte + 3rd Byte+ 4th Byte}
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DONE = 3'd8;
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endmodule
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