forked from tanchou/Verilog
27 lines
462 B
Coq
27 lines
462 B
Coq
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`timescale 1ns/1ps
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module tb_dht11;
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reg clk = 0;
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always #18.5 clk = ~clk; // Génère une clock 27 MHz
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// === Simulation du module DHT11 ===
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// === Module DHT11 INTERFACE ===
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// === TEST SEQUENCE ===
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initial begin
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$dumpfile("runs/wave.vcd");
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$dumpvars(0, tb_dht11);
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$display("==== Start DHT11 Test ====");
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$display("==== End DHT11 Test ====");
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$finish;
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end
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endmodule
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