verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity
Files
20cbaace0879e4fcd9c3c871beb80052e7aeef8c
Verilog_Louis/Help/presentation_examples/led_walk/constraints/blink_leds.sdc

2 lines
81 B
Plaintext
Raw Normal View History

struct
2025-05-02 15:51:18 +02:00
create_clock -name clk_27M -period 37.037 -waveform {0 18.518} [get_ports {clk}]
Copy Permalink