forked from tanchou/Verilog
14 lines
288 B
Coq
14 lines
288 B
Coq
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module top_module(
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input [2:0] a,
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input [2:0] b,
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output [2:0] out_or_bitwise,
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output out_or_logical,
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output [5:0] out_not
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);
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assign out_or_bitwise = a | b;
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assign out_or_logical = a || b;
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assign out_not[2:0] = ~a;
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assign out_not[5:3] = ~b;
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endmodule
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