forked from tanchou/Verilog
7 lines
154 B
Coq
7 lines
154 B
Coq
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module top_module (
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input [4:0] a, b, c, d, e, f,
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output [7:0] w, x, y, z );//
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assign { w, x, y, z } = { a, b, c, d, e, f, 2'b11};
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endmodule
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