forked from tanchou/Verilog
14 lines
246 B
Coq
14 lines
246 B
Coq
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module top_module (
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input wire [2:0] vec,
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output wire [2:0] outv,
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output wire o2,
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output wire o1,
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output wire o0 );
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assign outv = vec;
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assign o0 = vec[0];
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assign o1 = vec[1];
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assign o2 = vec[2];
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endmodule
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