forked from tanchou/Verilog
46 lines
1.3 KiB
Batchfile
46 lines
1.3 KiB
Batchfile
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@echo off
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setlocal
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rem === Aller à la racine du projet ===
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cd /d %~dp0\..
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rem === Config de base ===
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set DEVICE=GW2AR-LV18QN88C8/I7
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set BOARD=tangnano20k
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set TOP=top_uart_ultrason_command
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set CST_FILE=%TOP%.cst
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set JSON_FILE=runs/%TOP%.json
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set PNR_JSON=runs/pnr_%TOP%.json
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set BITSTREAM=runs/%TOP%.fs
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rem === Créer le dossier runs si nécessaire ===
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if not exist runs (
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mkdir runs
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)
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echo === Étape 1 : Synthèse avec Yosys ===
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yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
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if errorlevel 1 goto error
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echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
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nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
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if errorlevel 1 goto error
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echo === Étape 3 : Packing avec gowin_pack ===
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gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
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if errorlevel 1 goto error
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echo === Étape 4 : Flash avec openFPGALoader ===
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openFPGALoader -b %BOARD% %BITSTREAM%
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if errorlevel 1 goto error
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echo === Compilation et flash réussis ===
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goto end
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:error
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echo === Une erreur est survenue ===
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:end
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endlocal
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pause
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