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Verilog_Louis/Semaine_4/UART/src/verilog/top_uart_loopback.v

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2025-05-05 14:52:01 +02:00
module top_uart_loopback (
input wire clk, // 27 MHz
input wire rx,
output wire tx,
output reg [5:0] leds
);
wire rx_received;
wire [7:0] rx_data;
reg [7:0] tx_data;
reg tx_enable;
wire tx_ready;
initial begin
leds = 6'b000000; // Initialiser les LEDs à 0
end
// === UART RX ===
uart_rx uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_pin(rx),
.rx_received(rx_received),
.rx_enable(1'b1),
.rx_data(rx_data)
);
// === UART TX ===
uart_tx uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(tx_data),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx)
);
// === FSM pour déclencher la transmission ===
localparam IDLE = 0, SEND = 1;
reg state = IDLE;
always @(posedge clk) begin
case (state)
IDLE: begin
tx_enable <= 0;
if (rx_received && tx_ready) begin
tx_data <= rx_data;
tx_enable <= 1;
state <= SEND;
leds[0] <= 1;
leds[5:1] <= 0;
end
end
SEND: begin
tx_enable <= 0;
state <= IDLE;
leds[0] <= 0; // LED 0 allumée pour indiquer la réception
leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission
end
endcase
end
endmodule