forked from tanchou/Verilog
67 lines
1.5 KiB
Coq
67 lines
1.5 KiB
Coq
![]() |
module top_uart_loopback (
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input wire clk, // 27 MHz
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input wire rx,
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output wire tx,
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output reg [5:0] leds
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);
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wire rx_received;
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wire [7:0] rx_data;
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reg [7:0] tx_data;
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reg tx_enable;
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wire tx_ready;
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initial begin
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leds = 6'b000000; // Initialiser les LEDs à 0
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end
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// === UART RX ===
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uart_rx uart_rx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.rx_pin(rx),
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.rx_received(rx_received),
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.rx_enable(1'b1),
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.rx_data(rx_data)
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);
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// === UART TX ===
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.data(tx_data),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx(tx)
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);
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// === FSM pour déclencher la transmission ===
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localparam IDLE = 0, SEND = 1;
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reg state = IDLE;
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always @(posedge clk) begin
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case (state)
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IDLE: begin
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tx_enable <= 0;
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if (rx_received && tx_ready) begin
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tx_data <= rx_data;
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tx_enable <= 1;
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state <= SEND;
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leds[0] <= 1;
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leds[5:1] <= 0;
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end
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end
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SEND: begin
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tx_enable <= 0;
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state <= IDLE;
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leds[0] <= 0; // LED 0 allumée pour indiquer la réception
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leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission
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end
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endcase
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end
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endmodule
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