Verilog_Louis/Semaine_4/FIFO/src/verilog/fifo.v

 module uart_tx #(
	parameter       DETPH = 16,
	parameter       WIDTH = 8
)(
    input wire              clk,
    input wire              wr_en,
    input wire[WIDTH-1:0]   wr_data,
    input wire              rd_en,
    output wire[WIDTH-1:0]  rd_data,

    output wire             full,
    output wire             empty,
);

    
endmodule