forked from tanchou/Verilog
110 lines
698 B
Plaintext
110 lines
698 B
Plaintext
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$date
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Sat Mar 22 10:16:37 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module tb_counter $end
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$scope module counter_inst $end
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$var wire 1 ! clk $end
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$var wire 1 " rst $end
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$var reg 4 # count [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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bx #
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0"
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0!
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$end
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#5
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0!
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#10
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0!
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#15
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0!
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#20
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b0 #
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0!
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1"
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#25
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0!
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#30
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0!
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#35
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0!
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#40
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0!
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#45
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0!
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#50
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0!
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#55
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0!
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#60
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0!
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#65
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0!
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#70
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0!
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#75
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0!
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#80
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0!
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#85
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0!
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#90
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0!
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#95
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0!
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#100
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b1 #
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0!
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0"
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#105
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b10 #
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0!
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#110
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b11 #
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0!
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#115
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b100 #
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0!
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#120
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b101 #
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0!
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#125
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b110 #
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0!
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#130
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b111 #
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0!
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#135
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b1000 #
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0!
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#140
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b1001 #
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0!
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#145
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b1010 #
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0!
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#150
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b0 #
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0!
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1"
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#155
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0!
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#160
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0!
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#165
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0!
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#170
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0!
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