forked from tanchou/Verilog
47 lines
1.3 KiB
Bash
47 lines
1.3 KiB
Bash
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#!/bin/bash
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# Aller à la racine du projet
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cd "$(dirname "$0")/../.." || exit 1
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# Config de base
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DEVICE="GW2AR-LV18QN88C8/I7"
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BOARD="tangnano20k"
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TOP="top_uart_ultrason_command"
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CST_FILE="$TOP.cst"
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JSON_FILE="runs/$TOP.json"
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PNR_JSON="runs/pnr_$TOP.json"
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BITSTREAM="runs/$TOP.fs"
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# Créer le dossier runs si nécessaire
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mkdir -p runs
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echo "=== Étape 1 : Synthèse avec Yosys ==="
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yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top $TOP -json $JSON_FILE"
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if [ $? -ne 0 ]; then
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echo "=== Erreur lors de la synthèse ==="
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exit 1
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fi
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echo "=== Étape 2 : Placement & Routage avec nextpnr-himbaechel ==="
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nextpnr-himbaechel --json "$JSON_FILE" --write "$PNR_JSON" --device "$DEVICE" --vopt cst=constraints/"$CST_FILE" --vopt family=GW2A-18C
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if [ $? -ne 0 ]; then
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echo "=== Erreur lors du placement/routage ==="
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exit 1
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fi
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echo "=== Étape 3 : Packing avec gowin_pack ==="
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gowin_pack -d "$DEVICE" -o "$BITSTREAM" "$PNR_JSON"
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if [ $? -ne 0 ]; then
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echo "=== Erreur lors du packing ==="
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exit 1
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fi
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echo "=== Étape 4 : Flash avec openFPGALoader ==="
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openFPGALoader -b "$BOARD" "$BITSTREAM"
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if [ $? -ne 0 ]; then
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echo "=== Erreur lors du flash ==="
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exit 1
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fi
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echo "=== Compilation et flash réussis ==="
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