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Verilog_Louis
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aaebf22d484871784907b71daa847c6c204994f5
Verilog_Louis
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Semaine_4
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FIFO
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scripts
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gtkwave.bat
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Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
@
echo
off
echo
=== Lancement de GTKWave ===
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
gtkwave runs/fifo.vcd
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