Verilog_Louis/Semaine_4/UART/tests/verilog/tb_uart_tx.v

`timescale 1ns/1ps

module tb_uart_tx;

    reg clk = 0;
    reg tx_enable = 0;
    reg [7:0] data_in = 8'h00;
    reg [7:0] data_out;
    wire tx;
    reg tx_ready;

    wire rx_recieved;

    always #18.5 clk = ~clk;

    uart_rx rx_instance(
        .clk(clk),
        .rx_pin(tx), // tx is connected to rx for testing
        .rst_n(1'b1),
        .rx_data(data_out),
        .rx_data_valid(rx_recieved),
        .rx_data_ready(1'b1)
    );

    uart_tx #(
        .CLK_FREQ(27_000_000),
        .BAUD_RATE(115_200)
    )tx_instance (
        .clk(clk),
        .tx_enable(tx_enable),
        .tx_ready(tx_ready),
        .data(data_in),
        .tx(tx),
        .rst_p(1'b0)
    );

    initial begin
        $dumpfile("runs/uart_tx.vcd");
        $dumpvars(0, tb_uart_tx);

        #100;

        data_in <= 8'd234;   // 234
        tx_enable <= 1;
        wait(tx_ready == 1'b0); 
        tx_enable <= 0; 

        // Attendre
        wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif

        $display("Data received: %d", data_out); // Afficher la valeur recu
        $display("Data expected: %d", data_in); // Afficher la valeur envoyee

        #1000;

        wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif

        data_in <= 8'd202;   // 202
        tx_enable <= 1;
        wait(tx_ready == 1'b0); 
        tx_enable <= 0; 

        // Attendre
        wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif

        $display("Data received: %d", data_out); // Afficher la valeur recu
        $display("Data expected: %d", data_in); // Afficher la valeur envoyee

        #1000;
        $stop;
    end

endmodule