forked from tanchou/Verilog
4 lines
126 B
Plaintext
4 lines
126 B
Plaintext
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IO_LOC "led" 15;
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IO_PORT "led" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "clk" 4;
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IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;
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