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Verilog_Louis/Help/presentation_examples/counter/verification/counter1.sby

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2025-05-02 15:51:18 +02:00
[tasks]
bmc
prove
cover
[options]
bmc: mode bmc
prove: mode prove
cover: mode cover
bmc: depth 100
[engines]
smtbmc
#smtbmc z3
#abc bmc3
[script]
read -verific
read -sv counter.v
read -formal counter_formal.sv
prep -top counter
[files]
../src/verilog/counter.v
counter_formal.sv