verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Add README for UART loopback issue and delay explanation

Browse Source
This commit is contained in:
Gamenight77
2025-05-09 11:58:55 +02:00
parent e086ba8ef0
commit 004def5ba2
1 changed files with 5 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
Semaine_4/UART_FIFO/README.md Normal file
View File

@@ -0,0 +1,5 @@
# UART loopback
Probleme
3 octest de retard
quand vous envoyer un octet, vous recevez le loopback de 3 octets plus tot. il faut attendre 3 octets avant de le recevoir