From 0f14bf24a6cc7056c38980daff8490191e21f574 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Thu, 29 May 2025 10:44:03 +0200 Subject: [PATCH] Update PLL configuration in fpga_wifi_led module for Tang Nano 9K board --- .../ESP32/leds_commands/src/verilog/fpga_wifi_led.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v b/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v index 1e3a444..448792f 100644 --- a/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v +++ b/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v @@ -31,14 +31,14 @@ module fpga_wifi_led ( wire out_clk; wire clk_lock; - PLLVR #( // For GW1NSR-4C C6/I5 (Tang Nano 4K proto dev board) + rPLL #( // For GW1NR-9C C6/I5 (Tang Nano 9K proto dev board) .FCLKIN("27"), .IDIV_SEL(6), // -> PFD = 3.857142857142857 MHz (range: 3-400 MHz) - .FBDIV_SEL(25), // -> CLKOUT = 100.28571428571429 MHz (range: 4.6875-600 MHz) - .ODIV_SEL(8) // -> VCO = 802.2857142857143 MHz (range: 600-1200 MHz) - ) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0), .VREN(1'b1), + .FBDIV_SEL(14), // -> CLKOUT = 50.142857142857146 MHz (range: 3.125-600 MHz) + .ODIV_SEL(16) // -> VCO = 401.14285714285717 MHz (range: 400-1200 MHz) + ) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0), .CLKIN(i_clk), // 27 MHz - .CLKOUT(out_clk), // 100.28571428571429 MHz + .CLKOUT(out_clk), // 50.142857142857146 MHz .LOCK(clk_lock) );