From 1006b77e95989f9ef15a6bee41597fa380b66a52 Mon Sep 17 00:00:00 2001
From: Gamenight77 <game.night.77176@gmail.com>
Date: Mon, 19 May 2025 09:31:53 +0200
Subject: [PATCH] Update testbench and simulation scripts to use a unified
 output file name for GTKWave

---
 Semaine_4/UART_FIFO/scripts/gtkwave.bat             | 2 +-
 Semaine_4/UART_FIFO/scripts/simulate.bat            | 2 +-
 Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v    | 2 +-
 Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v | 4 ++--
 Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Semaine_4/UART_FIFO/scripts/gtkwave.bat b/Semaine_4/UART_FIFO/scripts/gtkwave.bat
index 4e7673e..0b86154 100644
--- a/Semaine_4/UART_FIFO/scripts/gtkwave.bat
+++ b/Semaine_4/UART_FIFO/scripts/gtkwave.bat
@@ -1,3 +1,3 @@
 @echo off
 echo === Lancement de GTKWave ===
-gtkwave runs/uart_tx_fifo.vcd
+gtkwave runs/sim.vcd
diff --git a/Semaine_4/UART_FIFO/scripts/simulate.bat b/Semaine_4/UART_FIFO/scripts/simulate.bat
index 54604a3..439cda3 100644
--- a/Semaine_4/UART_FIFO/scripts/simulate.bat
+++ b/Semaine_4/UART_FIFO/scripts/simulate.bat
@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
 set OUT=runs/sim.vvp
 
 :: Top-level testbench module
-set TOP=tb_uart_tx_fifo
+set TOP=tb_uart_rx_fifo
 
 :: Répertoires contenant des fichiers .v
 set DIRS=src/verilog tests/verilog IP/verilog
diff --git a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
index 1065fd6..2f09760 100644
--- a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
+++ b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
@@ -45,7 +45,7 @@ module tb_uart_fifo;
     );
 
     initial begin
-        $dumpfile("runs/uart_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_fifo);
 
         $display("======== Start UART LOOPBACK test =========");
diff --git a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
index ed2109b..fb16427 100644
--- a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
+++ b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
@@ -42,7 +42,7 @@ module tb_uart_rx_fifo;
     always #(CLK_PERIOD_NS/2) clk = ~clk;
 
     initial begin
-        $dumpfile("runs/uart_rx_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_rx_fifo);
         $display("======== Start UART RX FIFO test =========");
         #100; 
@@ -69,7 +69,7 @@ module tb_uart_rx_fifo;
 
         data_in = 8'd101; // Data to send
         wait(tx_data_ready); // Wait for the transmitter to be ready
-        #1; // Small delay to ensure the data is latched
+        
 
         tx_data_valid = 1'b1; // Indicate that the data is valid
 
diff --git a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
index 5be5b42..c8c0d52 100644
--- a/Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
+++ b/Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
@@ -39,7 +39,7 @@ module tb_uart_tx_fifo;
     );
 
     initial begin
-        $dumpfile("runs/uart_tx_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_tx_fifo);
 
         $display("======== Start UART TX FIFO test =========");