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Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py

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This commit is contained in:
Gamenight77
2025-05-28 14:47:38 +02:00
parent b2d280b4e2
commit 12ce0d38a7
3 changed files with 23 additions and 7 deletions
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2
Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino
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@@ -20,7 +20,7 @@ bool touchDetected = false;
// UART pins for FPGA communication // UART pins for FPGA communication
const int UART_RX_PIN = 16; // GPIO16 - RX from FPGA const int UART_RX_PIN = 16; // GPIO16 - RX from FPGA
const int UART_TX_PIN = 17; // GPIO17 - TX to FPGA const int UART_TX_PIN = 17; // GPIO17 - TX to FPGA
const int UART_BAUD = 115200; const int UART_BAUD = 1000000;
void setup() { void setup() {
// Initialize Serial for USB debugging (115200 baud) // Initialize Serial for USB debugging (115200 baud)

26
Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
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@@ -5,10 +5,11 @@ module fpga_wifi_led (
output o_tx, output o_tx,
output [5:0] o_leds output [5:0] o_leds
); );
// === PARAMÈTRES === // === PARAMÈTRES ===
localparam CLK_FREQ = 27_000_000; localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115200; localparam BAUD_RATE = 1000000;
localparam FIFO_SIZE = 8; localparam FIFO_SIZE = 8;
// === SIGNAUX UART RX === // === SIGNAUX UART RX ===
@@ -26,6 +27,21 @@ module fpga_wifi_led (
reg [1:0] state; reg [1:0] state;
reg [7:0] received_byte; reg [7:0] received_byte;
wire out_clk;
wire clk_lock;
PLLVR #( // For GW1NSR-4C C6/I5 (Tang Nano 4K proto dev board)
.FCLKIN("27"),
.IDIV_SEL(6), // -> PFD = 3.857142857142857 MHz (range: 3-400 MHz)
.FBDIV_SEL(12), // -> CLKOUT = 50.142857142857146 MHz (range: 4.6875-600 MHz)
.ODIV_SEL(16) // -> VCO = 802.2857142857143 MHz (range: 600-1200 MHz)
) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0), .VREN(1'b1),
.CLKIN(i_clk), // 27 MHz
.CLKOUT(out_clk), // 50.142857142857146 MHz
.LOCK(clk_lock)
);
// === ÉTATS DE LA FSM === // === ÉTATS DE LA FSM ===
localparam IDLE = 2'd0, localparam IDLE = 2'd0,
WAIT_BYTE = 2'd1, WAIT_BYTE = 2'd1,
@@ -38,7 +54,7 @@ module fpga_wifi_led (
.BAUD_RATE(BAUD_RATE), .BAUD_RATE(BAUD_RATE),
.FIFO_SIZE(FIFO_SIZE) .FIFO_SIZE(FIFO_SIZE)
) uart_rx_inst ( ) uart_rx_inst (
.clk(i_clk), .clk(out_clk),
.rd_en(rx_rd_en), .rd_en(rx_rd_en),
.rd_data(rx_data), .rd_data(rx_data),
.rx_pin(i_rx), .rx_pin(i_rx),
@@ -51,7 +67,7 @@ module fpga_wifi_led (
.BAUD_RATE(BAUD_RATE), .BAUD_RATE(BAUD_RATE),
.FIFO_SIZE(FIFO_SIZE) .FIFO_SIZE(FIFO_SIZE)
) uart_tx_inst ( ) uart_tx_inst (
.clk(i_clk), .clk(out_clk),
.wr_en(tx_wr_en), .wr_en(tx_wr_en),
.wr_data(tx_data), .wr_data(tx_data),
.tx_pin(o_tx), .tx_pin(o_tx),
@@ -74,7 +90,7 @@ module fpga_wifi_led (
end end
// === MACHINE D'ÉTAT PRINCIPALE === // === MACHINE D'ÉTAT PRINCIPALE ===
always @(posedge i_clk) begin always @(posedge out_clk) begin
// Désactiver les signaux de contrôle par défaut // Désactiver les signaux de contrôle par défaut
rx_rd_en <= 0; rx_rd_en <= 0;
tx_wr_en <= 0; tx_wr_en <= 0;
@@ -82,7 +98,7 @@ module fpga_wifi_led (
case (state) case (state)
IDLE: begin IDLE: begin
received_byte <= 8'h00; received_byte <= 8'h00;
leds_reg[2:0] <= 3'b100;
if (rx_data_available) begin if (rx_data_available) begin
state <= WAIT_BYTE; state <= WAIT_BYTE;
end end

2
Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py
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@@ -24,5 +24,5 @@ def send_bytes(commands):
print("Erreur :", e) print("Erreur :", e)
# Exemple d'envoi # Exemple d'envoi
commands = [0x02] # Tu peux aussi faire ["0x01", "0x96", "0xA4"] commands = [0x01]
send_bytes(commands) send_bytes(commands)