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Code FPGA fonctionnel

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Gamenight77
2025-05-27 15:36:40 +02:00
parent 4e16bb3cbe
commit 168431849b
24 changed files with 2038 additions and 4 deletions
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6
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -120,10 +120,8 @@ module dht11_interface #(
timer <= timer + 1;
if (sig_in == 1 ) begin
timer <= 0;
state <= RESPONSE_HIGH;
end
end
@@ -132,8 +130,8 @@ module dht11_interface #(
o_state <= state;
if (sig_in == 0) begin
timer <= 0;
state <= READ_BITS_LOW;
timer <= 0;
state <= READ_BITS_LOW;
end
end