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Code FPGA fonctionnel

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Gamenight77
2025-05-27 15:36:40 +02:00
parent 4e16bb3cbe
commit 168431849b
24 changed files with 2038 additions and 4 deletions
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21
Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst Normal file
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IO_LOC "o_tx" 69;
IO_PORT "o_tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_rx" 70;
IO_PORT "i_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_clk" 4;
IO_PORT "i_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "o_leds[0]" 15;
IO_PORT "o_leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "o_leds[1]" 16;
IO_PORT "o_leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "o_leds[2]" 17;
IO_PORT "o_leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "o_leds[3]" 18;
IO_PORT "o_leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "o_leds[4]" 19;
IO_PORT "o_leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "o_leds[5]" 20;
IO_PORT "o_leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;