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Création de la structure du uart fifo

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Gamenight77
2025-05-06 09:42:26 +02:00
parent aaebf22d48
commit 1ca3456ab8
17 changed files with 758 additions and 12 deletions
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41
Semaine_4/UART/src/verilog/top_uart_loopback.v
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@@ -13,7 +13,7 @@ module top_uart_loopback (
wire tx_ready;
initial begin
leds = 6'b000000; // Initialiser les LEDs à 0
leds = 6'b111111;
end
// === UART RX ===
@@ -36,32 +36,51 @@ module top_uart_loopback (
.tx(tx)
);
// === FSM pour déclencher la transmission ===
localparam IDLE = 0, SEND = 1;
reg state = IDLE;
// === FSM avec délai ===
localparam IDLE = 0, WAIT = 1, SEND = 2;
reg [1:0] state = IDLE;
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
leds[5] <= rx;
leds[4] <= tx;
case (state)
IDLE: begin
tx_enable <= 0;
delay_counter <= 0;
if (rx_received && tx_ready) begin
tx_data <= rx_data;
tx_enable <= 1;
state <= SEND;
leds[0] <= 1;
leds[5:1] <= 0;
state <= WAIT;
leds[0] <= 0;
leds[1] <= 1;
end
end
WAIT: begin
delay_counter <= delay_counter + 1;
if (delay_counter == 8'd400 && tx_ready) begin
tx_enable <= 1;
state <= SEND;
end else begin
tx_enable <= 0;
end
leds[0] <= 1;
leds[1] <= 0;
end
SEND: begin
tx_enable <= 0;
state <= IDLE;
leds[0] <= 0; // LED 0 allumée pour indiquer la réception
leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission
leds[0] <= 0;
leds[1] <= 0; // Envoi terminé
end
endcase
end
endmodule
endmodule

2
Semaine_4/UART/src/verilog/uart_tx.v
View File

@@ -84,7 +84,7 @@ module uart_tx #(
if(rst_p == 1'b1) begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_enable == 1'b1) begin
tx_data_latch <= data; // Charger les données de `data` dans `tx_data_latch`
tx_data_latch <= data; // Charger les données de data dans tx_data_latch
end
end