verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Création de la structure du uart fifo

Browse Source
This commit is contained in:
Gamenight77
2025-05-06 09:42:26 +02:00
parent aaebf22d48
commit 1ca3456ab8
17 changed files with 758 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
Semaine_4/UART_FIFO/constraints/top_uart_loopback.cst Normal file
View File

@@ -0,0 +1,19 @@
IO_LOC "rx" 70;
IO_PORT "rx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "tx" 69;
IO_PORT "tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;