forked from tanchou/Verilog
Création de la structure du uart fifo
This commit is contained in:
Gamenight77
67
Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v
Normal file
67
Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v
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@@ -0,0 +1,67 @@
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module top_uart_loopback (
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input wire clk, // 27 MHz
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input wire rx,
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output wire tx,
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output reg [5:0] leds
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);
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wire rx_received;
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wire [7:0] rx_data;
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reg [7:0] tx_data;
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reg tx_enable;
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wire tx_ready;
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initial begin
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leds = 6'b000000; // Initialiser les LEDs à 0
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end
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// === UART RX ===
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uart_rx uart_rx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.rx_pin(rx),
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.rx_received(rx_received),
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.rx_enable(1'b1),
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.rx_data(rx_data)
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);
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// === UART TX ===
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.data(tx_data),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx(tx)
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);
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// === FSM pour déclencher la transmission ===
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localparam IDLE = 0, SEND = 1;
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reg state = IDLE;
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always @(posedge clk) begin
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leds[5] <= rx;
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case (state)
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IDLE: begin
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tx_enable <= 0;
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if (rx_received && tx_ready) begin
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tx_data <= rx_data;
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tx_enable <= 1;
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state <= SEND;
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leds[0] <= 1;
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leds[5:1] <= 0;
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end
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end
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SEND: begin
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tx_enable <= 0;
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state <= IDLE;
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leds[0] <= 0; // LED 0 allumée pour indiquer la réception
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leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission
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end
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endcase
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end
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endmodule
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145
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
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145
Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
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@@ -0,0 +1,145 @@
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module uart_rx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
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)(
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input clk, //clock input
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input rst_p, //asynchronous reset input, high active
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input rx_enable, //data receiver module ready
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input rx_pin, //serial data input
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output reg[7:0] rx_data, //received serial data
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output reg rx_received //received serial data is valid
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg[2:0] state;
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reg[2:0] next_state;
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reg rx_d0; //delay 1 clock for rx_pin
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
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reg[7:0] rx_bits; //temporary storage of received data
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
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always@(posedge clk or posedge rst_p) // Filtrage du signial
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begin
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if(rst_p == 1'b1)begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end else begin
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rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always@(posedge clk or posedge rst_p)begin // Compteur d'etat
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if(rst_p == 1'b1)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)begin
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case(state)
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S_IDLE:
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if(rx_negedge) // Detection du start bit
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next_state = S_START;
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else
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next_state = S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1) //one data cycle
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next_state = S_REC_BYTE;
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else
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next_state = S_START;
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S_REC_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
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next_state = S_STOP;
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else
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next_state = S_REC_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
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next_state = S_DATA;
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else
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next_state = S_STOP;
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S_DATA:
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if(rx_enable) //data receive complete
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next_state = S_IDLE;
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else
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next_state = S_DATA;
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default:
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next_state = S_IDLE;
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endcase
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_received <= 1'b0;
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else if(state == S_STOP && next_state != state)
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rx_received <= 1'b1;
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else if(state == S_DATA && rx_enable)
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rx_received <= 1'b0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_data <= 8'd0;
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else if(state == S_STOP && next_state != state)
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rx_data <= rx_bits;//latch received data
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_REC_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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cycle_cnt <= 16'd0;
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else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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//receive serial data bit data
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_bits <= 8'd0;
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else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
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rx_bits[bit_cnt] <= rx_pin;
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else
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rx_bits <= rx_bits;
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end
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endmodule
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131
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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131
Semaine_4/UART_FIFO/src/verilog/uart_tx_fifo.v
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@@ -0,0 +1,131 @@
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module uart_tx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
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)(
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input wire clk,
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input wire rst_p,
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input wire[7:0] data,
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input wire tx_enable,
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output reg tx_ready,
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output wire tx
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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localparam IDLE = 2'd0;
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localparam START = 2'd1;
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localparam DATA = 2'd2;
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localparam STOP = 2'd3;
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reg [1:0] state = IDLE;
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reg [1:0] next_state;
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reg [15:0] cycle_cnt; //baud counter
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reg tx_reg;
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reg [2:0] bit_cnt;
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reg [7:0] tx_data_latch = 0;
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assign tx = tx_reg;
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always@(posedge clk or posedge rst_p)begin // Avance d'etat
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if(rst_p == 1'b1)
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state <= IDLE;
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else
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state <= next_state;
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end
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always@(*) begin
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case(state)
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IDLE:
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if(tx_enable == 1'b1)
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next_state = START;
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else
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next_state = IDLE;
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START:
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if(cycle_cnt == CYCLE - 1)
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next_state = DATA;
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else
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next_state = START;
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DATA:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
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next_state = STOP;
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else
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next_state = DATA;
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STOP:
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if(cycle_cnt == CYCLE - 1)
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next_state = IDLE;
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else
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next_state = STOP;
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default:
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next_state = IDLE;
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endcase
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end
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always@(posedge clk or posedge rst_p)begin // tx_ready block
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if(rst_p == 1'b1)
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tx_ready <= 1'b0; // Reset
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else if(state == IDLE && tx_enable == 1'b1)
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tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
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else if(state == IDLE)
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tx_ready <= 1'b1;
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else if(state == STOP && cycle_cnt == CYCLE - 1)
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tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
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else
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tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
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end
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always@(posedge clk or posedge rst_p) begin // tx_data_latch block
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if(rst_p == 1'b1) begin
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tx_data_latch <= 8'd0;
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end else if(state == IDLE && tx_enable == 1'b1) begin
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tx_data_latch <= data; // Charger les données de `data` dans `tx_data_latch`
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end
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end
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always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
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if(rst_p == 1'b1)begin
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bit_cnt <= 3'd0;
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end else if(state == DATA)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or posedge rst_p)begin // Cycle counter
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if(rst_p == 1'b1)
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cycle_cnt <= 16'd0;
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else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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always@(posedge clk or posedge rst_p)begin // tx state managment
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if(rst_p == 1'b1)
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tx_reg <= 1'b1;
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else
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case(state)
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IDLE,STOP:
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tx_reg <= 1'b1;
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START:
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tx_reg <= 1'b0;
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DATA:
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tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
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default:
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tx_reg <= 1'b1;
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endcase
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end
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endmodule
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