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forked from tanchou/Verilog

Création de la structure du uart fifo

This commit is contained in:
Gamenight77
2025-05-06 09:42:26 +02:00
parent aaebf22d48
commit 1ca3456ab8
17 changed files with 758 additions and 12 deletions

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import serial
import time
# À adapter selon ton système
PORT = 'COM7' # ex: COM3 sur Windows ou /dev/ttyUSB0 sur Linux
BAUDRATE = 115200
TIMEOUT = 3 # en secondes
def main():
try:
with serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT) as ser:
print(f"[INFO] Connecté à {PORT} à {BAUDRATE} bauds.")
print("Tape un nombre entre 0 et 255. Ctrl+C pour quitter.\n")
while True:
user_input = input("Nombre à envoyer (0-255) : ")
if not user_input.isdigit():
print("⚠️ Entrée invalide. Tape un entier entre 0 et 255.")
continue
value = int(user_input)
if value < 0 or value >= 255:
print("⚠️ Valeur hors limites.")
continue
byte = bytes([value])
ser.write(byte)
print(f"[TX] Envoyé : {value} (0x{value:02X})")
time.sleep(0.01) # petite pause si nécessaire
rx = ser.read(1)
if rx:
print(f"[RX] Reçu : {int.from_bytes(rx, 'little')} (0x{rx.hex()})\n")
else:
print("⚠️ Aucun octet reçu (timeout ?)\n")
except serial.SerialException as e:
print(f"[ERREUR] Port série : {e}")
if __name__ == "__main__":
main()

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`timescale 1ns/1ps
module tb_uart;
reg clk = 0;
reg tx_enable = 0;
reg tx_ready;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
reg rx_received;
wire rx_enable = 1'b1;
wire pin;
always #18.5 clk = ~clk;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx_pin(pin),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
);
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
)tx_instance (
.clk(clk),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(pin),
.rst_p(1'b0)
);
initial begin
$dumpfile("runs/uart.vcd");
$dumpvars(0, tb_uart);
$display("======== Start UART LOOPBACK test =========");
#100;
data_in <= 8'd234; // 234
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
#1000;
$stop;
end
endmodule

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`timescale 1ns / 1ps
module tb_uart_rx;
reg clk = 0;
reg rx;
reg [7:0] data_in;
reg [7:0] data_out;
reg tx_data_valid;
reg tx_data_ready;
reg rx_received;
wire rx_enable = 1'b1; // Enable the receiver
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ;
other_uart_tx tx_instance (
.clk(clk),
.tx_pin(rx),
.tx_data(data_in),
.tx_data_valid(tx_data_valid),
.tx_data_ready(tx_data_ready),
.rst_n(1'b1)
);
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx_pin(rx),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
);
always #(CLK_PERIOD_NS/2) clk = ~clk;
initial begin
$dumpfile("runs/uart_rx.vcd");
$dumpvars(0, tb_uart_rx);
$display("======== Start UART RX test =========");
#100;
data_in = 8'd123; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
tx_data_valid = 1'b1; // Indicate that the data is valid
wait(tx_data_ready == 0);
tx_data_valid = 1'b0; // Clear the valid signal
wait(rx_received); // Wait for the receiver to receive the data
$display("Data sent: %d", data_in);
$display("Data received: %d", data_out); // Display the received data
$display("======== END UART RX test =========");
$finish;
end
endmodule

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`timescale 1ns/1ps
module tb_uart_tx;
reg clk = 0;
reg tx_enable = 0;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
wire tx;
reg tx_ready;
wire rx_recieved;
always #18.5 clk = ~clk;
other_uart_rx rx_instance(
.clk(clk),
.rx_pin(tx), // tx is connected to rx for testing
.rst_n(1'b1),
.rx_data(data_out),
.rx_data_valid(rx_recieved),
.rx_data_ready(1'b1)
);
uart_tx #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200)
)tx_instance (
.clk(clk),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(tx),
.rst_p(1'b0)
);
initial begin
$dumpfile("runs/uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
$display("======== Start UART TX test =========");
#100;
data_in <= 8'd234; // 234
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
#1000;
$stop;
end
endmodule