diff --git a/Semaine_4/FIFO/src/verilog/fifo.v b/Semaine_4/FIFO/src/verilog/fifo.v
index 9fe96d0..679b0b5 100644
--- a/Semaine_4/FIFO/src/verilog/fifo.v
+++ b/Semaine_4/FIFO/src/verilog/fifo.v
@@ -12,5 +12,26 @@
     output wire             empty,
 );
 
+    reg [WIDTH-1:0]         fifo[0:DETPH-1];
+    reg [3:0]               wr_ptr;
+    reg [3:0]               rd_ptr;
+    reg [3:0]               count;
+
+    assign full = (count == DETPH);
+    assign empty = (count == 0);
+    assign rd_data = fifo[rd_ptr];
+
+    always @(posedge clk) begin
+        if (wr_en && !full) begin
+            fifo[wr_ptr] <= wr_data;
+            wr_ptr <= (wr_ptr + 1) % DETPH;
+            count <= count + 1;
+        end
+
+        if (rd_en && !empty) begin
+            rd_ptr <= (rd_ptr + 1) % DETPH;
+            count <= count - 1;
+        end
+    end
     
 endmodule