From 1d6677d67d4ffd61c56c54bd6ad7a230f47231ea Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 14 May 2025 09:22:07 +0200 Subject: [PATCH] Init du DHT11 Interface --- .../pnr_top_ultrasonic_led.json | 20561 ---------- .../Capteur_recule_bidirectionel_V2/sim.out | 420 - .../top_ultrasonic_led.fs | 1358 - .../top_ultrasonic_led.json | 34178 ---------------- .../top_ultrasonic_led.vcd | 24762 ----------- Semaine_5/DHT11/.gitignore | 5 + Semaine_5/DHT11/README.md | 9 + .../DHT11/constraints/dht11_interface.cst | 24 + Semaine_5/DHT11/project.bat | 6 + Semaine_5/DHT11/scripts/build.bat | 45 + Semaine_5/DHT11/scripts/clean.bat | 4 + Semaine_5/DHT11/scripts/gtkwave.bat | 3 + Semaine_5/DHT11/scripts/simulate.bat | 29 + Semaine_5/DHT11/src/verilog/dht11_interface.v | 35 + Semaine_5/DHT11/tests/verilog/tb_dht11.v | 27 + 15 files changed, 187 insertions(+), 81279 deletions(-) delete mode 100644 Semaine_3/Capteur_recule_bidirectionel_V2/pnr_top_ultrasonic_led.json delete mode 100644 Semaine_3/Capteur_recule_bidirectionel_V2/sim.out delete mode 100644 Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.fs delete mode 100644 Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.json delete mode 100644 Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.vcd create mode 100644 Semaine_5/DHT11/.gitignore create mode 100644 Semaine_5/DHT11/README.md create mode 100644 Semaine_5/DHT11/constraints/dht11_interface.cst create mode 100644 Semaine_5/DHT11/project.bat create mode 100644 Semaine_5/DHT11/scripts/build.bat create mode 100644 Semaine_5/DHT11/scripts/clean.bat create mode 100644 Semaine_5/DHT11/scripts/gtkwave.bat create mode 100644 Semaine_5/DHT11/scripts/simulate.bat create mode 100644 Semaine_5/DHT11/src/verilog/dht11_interface.v create mode 100644 Semaine_5/DHT11/tests/verilog/tb_dht11.v diff --git a/Semaine_3/Capteur_recule_bidirectionel_V2/pnr_top_ultrasonic_led.json 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- } - } - } - } - } -} diff --git a/Semaine_3/Capteur_recule_bidirectionel_V2/sim.out b/Semaine_3/Capteur_recule_bidirectionel_V2/sim.out deleted file mode 100644 index 767a405..0000000 --- a/Semaine_3/Capteur_recule_bidirectionel_V2/sim.out +++ /dev/null @@ -1,420 +0,0 @@ -#! -:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision - 12; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi"; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi"; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi"; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi"; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi"; -:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2009.vpi"; -S_00000247b1636280 .scope package, "$unit" "$unit" 2 1; - .timescale 0 0; -S_00000247b1637ec0 .scope module, "tb_top_ultrasonic_led" "tb_top_ultrasonic_led" 3 3; - .timescale -9 -12; -o00000247b165a468 .functor BUFZ 1, c4; HiZ drive -; Elide local net with no drivers, v00000247b16ac1d0_0 name=_ivl_0 -v00000247b16ac8b0_0 .var "clk", 0 0; -v00000247b16ad5d0_0 .net "leds", 5 0, v00000247b162bdc0_0; 1 drivers -RS_00000247b165a108 .resolv tri, L_00000247b16acdb0, L_00000247b16ac590; -v00000247b16ac310_0 .net8 "sig", 0 0, RS_00000247b165a108; 2 drivers -v00000247b16ad2b0_0 .var "sig_drive_enable", 0 0; -v00000247b16ac3b0_0 .var "sig_driver", 0 0; -v00000247b16ada30_0 .var "start", 0 0; -E_00000247b1631690 .event anyedge, v00000247b162c5e0_0; -L_00000247b16acdb0 .functor MUXZ 1, o00000247b165a468, v00000247b16ac3b0_0, v00000247b16ad2b0_0, C4<>; -S_00000247b163de10 .scope module, "uut" "top_ultrasonic_led" 3 16, 4 1 0, S_00000247b1637ec0; - .timescale -9 -12; - .port_info 0 /INPUT 1 "clk"; - .port_info 1 /INPUT 1 "start"; - .port_info 2 /INOUT 1 "sig"; - .port_info 3 /OUTPUT 6 "leds"; -v00000247b162c0e0_0 .net "clk", 0 0, v00000247b16ac8b0_0; 1 drivers -v00000247b162c4a0_0 .net "distance", 15 0, v00000247b162c360_0; 1 drivers -v00000247b162c860_0 .net "leds", 5 0, v00000247b162bdc0_0; alias, 1 drivers -v00000247b162c900_0 .net8 "sig", 0 0, RS_00000247b165a108; alias, 2 drivers -v00000247b16ad3f0_0 .net "start", 0 0, v00000247b16ada30_0; 1 drivers -L_00000247b16add50 .part v00000247b162c360_0, 0, 9; -S_00000247b163dfa0 .scope module, "led_display_inst" "distance_display_led" 4 19, 5 1 0, S_00000247b163de10; - .timescale -9 -12; - .port_info 0 /INPUT 9 "distance"; - .port_info 1 /OUTPUT 6 "leds"; -P_00000247b1636410 .param/l "LEVELS" 0 5 9, +C4<00000000000000000000000000000101>; -P_00000247b1636448 .param/l "MAX_DIST" 0 5 8, +C4<00000000000000000000000101011101>; -P_00000247b1636480 .param/l "MIN_DIST" 0 5 7, +C4<00000000000000000000000000000010>; -P_00000247b16364b8 .param/l "PART_SIZE" 0 5 10, +C4<0000000000000000000000000001000101>; -v00000247b162c2c0_0 .net "distance", 8 0, L_00000247b16add50; 1 drivers -v00000247b162bdc0_0 .var "leds", 5 0; -E_00000247b1631f10 .event anyedge, v00000247b162c2c0_0; -S_00000247b163e130 .scope module, "ultrasonic_inst" "ultrasonic_fpga" 4 11, 6 1 0, S_00000247b163de10; - .timescale -9 -12; - .port_info 0 /INPUT 1 "clk"; - .port_info 1 /INPUT 1 "start"; - .port_info 2 /INOUT 1 "sig"; - .port_info 3 /OUTPUT 16 "distance"; - .port_info 4 /OUTPUT 3 "state"; -P_00000247b164fb50 .param/l "CLK_FREQ" 0 6 2, +C4<00000001100110111111110011000000>; -P_00000247b164fb88 .param/l "DIST_DIVISOR" 1 6 31, +C4<00000000000000000000011000011110>; -P_00000247b164fbc0 .param/l "DONE" 1 6 27, C4<101>; -P_00000247b164fbf8 .param/l "IDLE" 1 6 22, C4<000>; -P_00000247b164fc30 .param/l "MAX_CM" 1 6 32, +C4<00000000000000000000000101011110>; -P_00000247b164fc68 .param/l "MEASURE_ECHO" 1 6 26, C4<100>; -P_00000247b164fca0 .param/l "TIMEOUT_CYCLES" 1 6 33, +C4<11111111111111111111100110001001>; -P_00000247b164fcd8 .param/l "TRIG_HIGH" 1 6 23, C4<001>; -P_00000247b164fd10 .param/l "TRIG_LOW" 1 6 24, C4<010>; -P_00000247b164fd48 .param/l "TRIG_PULSE_CYCLES" 1 6 30, +C4<00000000000000000000000100001110>; -P_00000247b164fd80 .param/l "WAIT_ECHO" 1 6 25, C4<011>; -P_00000247b164fdb8 .param/l "WAIT_NEXT" 1 6 28, C4<110>; -P_00000247b164fdf0 .param/l "WAIT_NEXT_CYCLES" 1 6 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>; -o00000247b1659fe8 .functor BUFZ 1, c4; HiZ drive -; Elide local net with no drivers, v00000247b162c540_0 name=_ivl_0 -v00000247b162bd20_0 .net "clk", 0 0, v00000247b16ac8b0_0; alias, 1 drivers -v00000247b162c360_0 .var "distance", 15 0; -v00000247b162c9a0_0 .var "distance_counter", 15 0; -v00000247b162bf00_0 .var "echo_counter", 31 0; -v00000247b162c680_0 .var "echo_div_counter", 31 0; -v00000247b162c5e0_0 .net8 "sig", 0 0, RS_00000247b165a108; alias, 2 drivers -v00000247b162c720_0 .var "sig_dir", 0 0; -v00000247b162be60_0 .var "sig_int", 0 0; -v00000247b162ca40_0 .var "sig_ok", 0 0; -v00000247b162bbe0_0 .var "sig_out", 0 0; -v00000247b162bfa0_0 .net "start", 0 0, v00000247b16ada30_0; alias, 1 drivers -v00000247b162c400_0 .var "state", 2 0; -v00000247b162c040_0 .var "trig_counter", 15 0; -v00000247b162c7c0_0 .var "wait_counter", 31 0; -E_00000247b1631f90 .event posedge, v00000247b162bd20_0; -L_00000247b16ac590 .functor MUXZ 1, o00000247b1659fe8, v00000247b162bbe0_0, v00000247b162c720_0, C4<>; - .scope S_00000247b163e130; -T_0 ; - %wait E_00000247b1631f90; - %load/vec4 v00000247b162c5e0_0; - %assign/vec4 v00000247b162be60_0, 0; - %load/vec4 v00000247b162be60_0; - %assign/vec4 v00000247b162ca40_0, 0; - %jmp T_0; - .thread T_0; - .scope S_00000247b163e130; -T_1 ; - %wait E_00000247b1631f90; - %load/vec4 v00000247b162c400_0; - %dup/vec4; - %pushi/vec4 0, 0, 3; - %cmp/u; - %jmp/1 T_1.0, 6; - %dup/vec4; - %pushi/vec4 1, 0, 3; - %cmp/u; - %jmp/1 T_1.1, 6; - %dup/vec4; - %pushi/vec4 2, 0, 3; - %cmp/u; - %jmp/1 T_1.2, 6; - %dup/vec4; - %pushi/vec4 3, 0, 3; - %cmp/u; - %jmp/1 T_1.3, 6; - %dup/vec4; - %pushi/vec4 4, 0, 3; - %cmp/u; - %jmp/1 T_1.4, 6; - %dup/vec4; - %pushi/vec4 5, 0, 3; - %cmp/u; - %jmp/1 T_1.5, 6; - %dup/vec4; - %pushi/vec4 6, 0, 3; - %cmp/u; - %jmp/1 T_1.6, 6; - %pushi/vec4 0, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; - %jmp T_1.8; -T_1.0 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v00000247b162bbe0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v00000247b162c720_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v00000247b162c360_0, 0; - %load/vec4 v00000247b162bfa0_0; - %flag_set/vec4 8; - %jmp/0xz T_1.9, 8; - %pushi/vec4 1, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v00000247b162c040_0, 0; -T_1.9 ; - %jmp T_1.8; -T_1.1 ; - %pushi/vec4 1, 0, 1; - %assign/vec4 v00000247b162bbe0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v00000247b162c720_0, 0; - %load/vec4 v00000247b162c040_0; - %pad/u 32; - %cmpi/u 270, 0, 32; - %jmp/0xz T_1.11, 5; - %load/vec4 v00000247b162c040_0; - %addi 1, 0, 16; - %assign/vec4 v00000247b162c040_0, 0; - %jmp T_1.12; -T_1.11 ; - %pushi/vec4 0, 0, 16; - %assign/vec4 v00000247b162c040_0, 0; - %pushi/vec4 2, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; -T_1.12 ; - %jmp T_1.8; -T_1.2 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v00000247b162bbe0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v00000247b162c720_0, 0; - %pushi/vec4 3, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; - %jmp T_1.8; -T_1.3 ; - %load/vec4 v00000247b162ca40_0; - %flag_set/vec4 8; - %jmp/0xz T_1.13, 8; - %pushi/vec4 0, 0, 32; - %assign/vec4 v00000247b162bf00_0, 0; - %pushi/vec4 4, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; - %jmp T_1.14; -T_1.13 ; - %load/vec4 v00000247b162bf00_0; - %cmpi/u 4294965641, 0, 32; - %flag_inv 5; GE is !LT - %jmp/0xz T_1.15, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v00000247b162c360_0, 0; - %pushi/vec4 5, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; - %jmp T_1.16; -T_1.15 ; - %load/vec4 v00000247b162bf00_0; - %addi 1, 0, 32; - %assign/vec4 v00000247b162bf00_0, 0; -T_1.16 ; -T_1.14 ; - %jmp T_1.8; -T_1.4 ; - %load/vec4 v00000247b162ca40_0; - %flag_set/vec4 8; - %jmp/0xz T_1.17, 8; - %load/vec4 v00000247b162bf00_0; - %cmpi/u 4294965641, 0, 32; - %jmp/0xz T_1.19, 5; - %load/vec4 v00000247b162bf00_0; - %addi 1, 0, 32; - %assign/vec4 v00000247b162bf00_0, 0; - %jmp T_1.20; -T_1.19 ; - %pushi/vec4 0, 0, 16; - %assign/vec4 v00000247b162c360_0, 0; - %pushi/vec4 5, 0, 3; - %assign/vec4 v00000247b162c400_0, 0; -T_1.20 ; - %jmp T_1.18; -T_1.17 ; - %load/vec4 v00000247b162bf00_0; - %addi 1, 0, 32; - %assign/vec4 v00000247b162bf00_0, 0; - %load/vec4 v00000247b162c680_0; - %cmpi/u 1565, 0, 32; - %flag_inv 5; GE is !LT - %jmp/0xz T_1.21, 5; - %pushi/vec4 0, 0, 32; - %assign/vec4 v00000247b162c680_0, 0; - %load/vec4 v00000247b162c9a0_0; - %addi 1, 0, 16; - %assign/vec4 v00000247b162c9a0_0, 0; - %jmp T_1.22; -T_1.21 ; - %load/vec4 v00000247b162c680_0; - %addi 1, 0, 32; - %assign/vec4 v00000247b162c680_0, 0; -T_1.22 ; - %load/vec4 v00000247b162c9a0_0; - %assign/vec4 v00000247b162c360_0, 0; - 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a/Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.vcd +++ /dev/null @@ -1,24762 +0,0 @@ -$date - Fri Apr 25 16:09:06 2025 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module tb_top_ultrasonic_led $end -$var wire 1 ! sig $end -$var wire 6 " leds [5:0] $end -$var reg 1 # clk $end -$var reg 1 $ sig_drive_enable $end -$var reg 1 % sig_driver $end -$var reg 1 & start $end -$scope module uut $end -$var wire 1 # clk $end -$var wire 1 ! sig $end -$var wire 1 & start $end -$var wire 6 ' leds [5:0] $end -$var wire 16 ( distance [15:0] $end -$scope module led_display_inst $end -$var wire 9 ) distance [8:0] $end -$var parameter 32 * LEVELS $end -$var parameter 32 + MAX_DIST $end -$var parameter 32 , MIN_DIST $end -$var parameter 34 - PART_SIZE $end -$var reg 6 . leds [5:0] $end -$upscope $end -$scope module ultrasonic_inst $end -$var wire 1 # clk $end -$var wire 1 ! sig $end -$var wire 1 & start $end -$var parameter 32 / CLK_FREQ $end -$var parameter 32 0 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b/Semaine_5/DHT11/README.md @@ -0,0 +1,9 @@ +# ULTRASON VIA UART + +## Description +This project is designed to control an ultrasonic sensor using UART communication. The ultrasonic sensor is used to measure distance, and the data is transmitted via UART to a connected device. + +## Commands +0x01: Start one mesurement of the distance. +0x02: Start continuous mesurement of the distance. +0x03: Stop continuous mesurement of the distance. \ No newline at end of file diff --git a/Semaine_5/DHT11/constraints/dht11_interface.cst b/Semaine_5/DHT11/constraints/dht11_interface.cst new file mode 100644 index 0000000..110a02b --- /dev/null +++ b/Semaine_5/DHT11/constraints/dht11_interface.cst @@ -0,0 +1,24 @@ +IO_LOC "tx" 69; +IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; + +IO_LOC "rx" 70; +IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; + +IO_LOC "clk" 4; +IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3; + +IO_LOC "ultrason_sig" 73; +IO_PORT "ultrason_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; + +IO_LOC "leds[0]" 15; +IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[1]" 16; +IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[2]" 17; +IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[3]" 18; +IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[4]" 19; +IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[5]" 20; +IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; \ No newline at end of file diff --git a/Semaine_5/DHT11/project.bat b/Semaine_5/DHT11/project.bat new file mode 100644 index 0000000..6998748 --- /dev/null +++ b/Semaine_5/DHT11/project.bat @@ -0,0 +1,6 @@ +@call c:\oss-cad-suite\environment.bat +@echo off +if "%1"=="sim" call scripts\simulate.bat +if "%1"=="wave" call scripts\gtkwave.bat +if "%1"=="clean" call scripts\clean.bat +if "%1"=="build" call scripts\build.bat diff --git a/Semaine_5/DHT11/scripts/build.bat b/Semaine_5/DHT11/scripts/build.bat new file mode 100644 index 0000000..89520d5 --- /dev/null +++ b/Semaine_5/DHT11/scripts/build.bat @@ -0,0 +1,45 @@ +@echo off +setlocal + +rem === Aller à la racine du projet === +cd /d %~dp0\.. + +rem === Config de base === +set DEVICE=GW2AR-LV18QN88C8/I7 +set BOARD=tangnano20k +set TOP=top_uart_ultrason_command +set CST_FILE=%TOP%.cst +set JSON_FILE=runs/%TOP%.json +set PNR_JSON=runs/pnr_%TOP%.json +set BITSTREAM=runs/%TOP%.fs + +rem === Créer le dossier runs si nécessaire === +if not exist runs ( + mkdir runs +) + +echo === Étape 1 : Synthèse avec Yosys === +yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +if errorlevel 1 goto error + +echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === +nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C +if errorlevel 1 goto error + +echo === Étape 3 : Packing avec gowin_pack === +gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON% +if errorlevel 1 goto error + +echo === Étape 4 : Flash avec openFPGALoader === +openFPGALoader -b %BOARD% %BITSTREAM% +if errorlevel 1 goto error + +echo === Compilation et flash réussis === +goto end + +:error +echo === Une erreur est survenue === + +:end +endlocal +pause diff --git a/Semaine_5/DHT11/scripts/clean.bat b/Semaine_5/DHT11/scripts/clean.bat new file mode 100644 index 0000000..6192ae1 --- /dev/null +++ b/Semaine_5/DHT11/scripts/clean.bat @@ -0,0 +1,4 @@ +@echo off +echo === Nettoyage du dossier runs === +rd /s /q runs +mkdir runs diff --git a/Semaine_5/DHT11/scripts/gtkwave.bat b/Semaine_5/DHT11/scripts/gtkwave.bat new file mode 100644 index 0000000..c4180e0 --- /dev/null +++ b/Semaine_5/DHT11/scripts/gtkwave.bat @@ -0,0 +1,3 @@ +@echo off +echo === Lancement de GTKWave === +gtkwave runs/wave.vcd diff --git a/Semaine_5/DHT11/scripts/simulate.bat b/Semaine_5/DHT11/scripts/simulate.bat new file mode 100644 index 0000000..020d5d2 --- /dev/null +++ b/Semaine_5/DHT11/scripts/simulate.bat @@ -0,0 +1,29 @@ +@echo off +echo === Simulation avec Icarus Verilog === +setlocal enabledelayedexpansion + +:: Dossier de sortie +set OUT=runs/sim.vvp + +:: Top-level testbench module +set TOP=dht11_interface + +:: Répertoires contenant des fichiers .v +set DIRS=src/verilog tests/verilog IP/verilog + +:: Variable pour stocker les fichiers +set FILES= + +:: Boucle sur chaque dossier +for %%D in (%DIRS%) do ( + for %%F in (%%D\*.v) do ( + set FILES=!FILES! %%F + ) +) + +:: Compilation avec Icarus Verilog +iverilog -g2012 -o %OUT% -s %TOP% %FILES% + +endlocal + +vvp runs/sim.vvp \ No newline at end of file diff --git a/Semaine_5/DHT11/src/verilog/dht11_interface.v b/Semaine_5/DHT11/src/verilog/dht11_interface.v new file mode 100644 index 0000000..70dd045 --- /dev/null +++ b/Semaine_5/DHT11/src/verilog/dht11_interface.v @@ -0,0 +1,35 @@ +module dht11_interface ( + input wire i_clk, // 27 MHz + inout wire io_dht11_sig, + output wire o_dht11_data_ready, + output wire [7:0] o_temp_data, + output wire [7:0] o_hum_data, + output wire o_dht11_error +); + + // === DHT11 INTERFACE === + // Le module DHT11 est connecté à la broche io_dht11_sig. + // La communication se fait en mode bidirectionnel. + + wire sig_dir; + wire sig_out; + + assign io_dht11_sig = sig_dir ? sig_out : 1'bz; + + + // === FSM === + localparam IDLE = 3'd0, // Pull up la ligne + + START = 3'd1, // Pull low 18ms + WAIT_RESPONSE = 3'd2, // Release la ligne (entre 20 et 40us) + + READ_HUM_INT = 3'd3, + READ_HUM_DEC = 3'd4; + READ_TEMP_INT = 3'd5, + READ_TEMP_DEC = 3'd6, + READ_CHECKSUM = 3'd7, // Last 8 bits of {1st Byte + 2nd Byte + 3rd Byte+ 4th Byte} + + DONE = 3'd8; + + +endmodule diff --git a/Semaine_5/DHT11/tests/verilog/tb_dht11.v b/Semaine_5/DHT11/tests/verilog/tb_dht11.v new file mode 100644 index 0000000..2bfe946 --- /dev/null +++ b/Semaine_5/DHT11/tests/verilog/tb_dht11.v @@ -0,0 +1,27 @@ +`timescale 1ns/1ps + +module tb_dht11; + + reg clk = 0; + always #18.5 clk = ~clk; // Génère une clock 27 MHz + + // === Simulation du module DHT11 === + + + // === Module DHT11 INTERFACE === + + + // === TEST SEQUENCE === + initial begin + $dumpfile("runs/wave.vcd"); + $dumpvars(0, tb_dht11); + + $display("==== Start DHT11 Test ===="); + + + + $display("==== End DHT11 Test ===="); + $finish; + end + +endmodule \ No newline at end of file