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Enhance DHT11 interface and update measurement delay in top module

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Gamenight77
2025-05-27 12:51:00 +02:00
parent 68000def79
commit 286ba6b33c
3 changed files with 34 additions and 9 deletions
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21
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -34,6 +34,7 @@ module dht11_interface #(
reg sig_in;
assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
// === REGISTRES ===
reg [3:0] state;
@@ -43,6 +44,8 @@ module dht11_interface #(
reg [5:0] bit_index;
reg [39:0] raw_data;
reg [15:0] checksum;
// === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms
@@ -155,9 +158,10 @@ module dht11_interface #(
raw_data <= {raw_data[38:0], (timer > T_40US)};
timer <= 0;
bit_index <= bit_index + 1;
if (bit_index == 39) begin
if (bit_index == 40) begin
state <= DONE;
end else begin
state <= READ_BITS_LOW;
@@ -168,12 +172,11 @@ module dht11_interface #(
DONE: begin
o_state <= state;
if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:24];
o_temp_data <= raw_data[23:8];
o_checksum <= raw_data[7:0];
o_dht11_data_ready <= 1;
end
o_hum_data <= raw_data[39:24];
o_temp_data <= raw_data[23:8];
o_checksum <= raw_data[7:0];
o_dht11_data_ready <= 1;
o_busy <= 0;
state <= IDLE;
@@ -182,4 +185,8 @@ module dht11_interface #(
endcase
end
always_comb begin
checksum = raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8];
end
endmodule