Enhance DHT11 interface and update measurement delay in top module

2025-05-27 12:51:00 +02:00
parent 68000def79
commit 286ba6b33c
3 changed files with 34 additions and 9 deletions
--- a/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
+++ b/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
@@ -60,9 +60,11 @@ initial begin
    leds = 6'b000000;
 end

-// 2s counter
+localparam MESURE_DELAY = 5; // 5 seconds delay for measurement
+
+// xs counter
 always_ff @(posedge clk) begin
-    if (delay_counter == CLK_FREQ * 2 - 1) begin
+    if (delay_counter == CLK_FREQ * MESURE_DELAY - 1) begin
        delay_counter <= 0;
        strobe2s <= 1;
    end else begin