verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Enhance DHT11 interface and update measurement delay in top module

Browse Source
This commit is contained in:
Gamenight77
2025-05-27 12:51:00 +02:00
parent 68000def79
commit 286ba6b33c
3 changed files with 34 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
View File

@@ -35,6 +35,7 @@ module dht11_interface #(
assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz) assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
// === REGISTRES === // === REGISTRES ===
reg [3:0] state; reg [3:0] state;
reg [31:0] timer; reg [31:0] timer;
@@ -43,6 +44,8 @@ module dht11_interface #(
reg [5:0] bit_index; reg [5:0] bit_index;
reg [39:0] raw_data; reg [39:0] raw_data;
reg [15:0] checksum;
// === FSM === // === FSM ===
localparam IDLE = 4'd0, // Pull up la ligne localparam IDLE = 4'd0, // Pull up la ligne
START = 4'd1, // Pull low 18ms START = 4'd1, // Pull low 18ms
@@ -155,9 +158,10 @@ module dht11_interface #(
raw_data <= {raw_data[38:0], (timer > T_40US)}; raw_data <= {raw_data[38:0], (timer > T_40US)};
timer <= 0; timer <= 0;
bit_index <= bit_index + 1; bit_index <= bit_index + 1;
if (bit_index == 39) begin if (bit_index == 40) begin
state <= DONE; state <= DONE;
end else begin end else begin
state <= READ_BITS_LOW; state <= READ_BITS_LOW;
@@ -168,12 +172,11 @@ module dht11_interface #(
DONE: begin DONE: begin
o_state <= state; o_state <= state;
if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:24]; o_hum_data <= raw_data[39:24];
o_temp_data <= raw_data[23:8]; o_temp_data <= raw_data[23:8];
o_checksum <= raw_data[7:0]; o_checksum <= raw_data[7:0];
o_dht11_data_ready <= 1; o_dht11_data_ready <= 1;
end
o_busy <= 0; o_busy <= 0;
state <= IDLE; state <= IDLE;
@@ -182,4 +185,8 @@ module dht11_interface #(
endcase endcase
end end
always_comb begin
checksum = raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8];
end
endmodule endmodule

6
Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
View File

@@ -60,9 +60,11 @@ initial begin
leds = 6'b000000; leds = 6'b000000;
end end
// 2s counter localparam MESURE_DELAY = 5; // 5 seconds delay for measurement
// xs counter
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (delay_counter == CLK_FREQ * 2 - 1) begin if (delay_counter == CLK_FREQ * MESURE_DELAY - 1) begin
delay_counter <= 0; delay_counter <= 0;
strobe2s <= 1; strobe2s <= 1;
end else begin end else begin

16
Semaine_7/ESP32/README.md Normal file
View File

@@ -0,0 +1,16 @@
#
Passerelle wifi
port série vitesse limité
réseau wifi plus rapide
but comm avec le fpga plus rapide et a distance
pour ce projet j'ai du apprendre le verilog pour utiliser le fpga
explqiuer le cheminenement d'evolution des projet
expliquer les soucis rencontrer (par exemple les timing)
expliquer que c'est long a cause des simulations (creation de model pour simuler le matos)
parfois en vrais les marges sont plus souple et ne respecte pas la doc
debuguage dure expliquer pourquoi