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Refactor ultrasonic_fpga module: improve code readability by adjusting comments and formatting in the Verilog file.

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Gamenight77
2025-04-22 14:38:50 +02:00
parent cb8b3c0c47
commit 2be0cb20f6
1 changed files with 3 additions and 3 deletions
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Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
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@@ -12,7 +12,7 @@ module ultrasonic_fpga #(
reg sig_out; reg sig_out;
reg sig_dir; // 1: output, 0: input reg sig_dir; // 1: output, 0: input
assign sig = sig_dir ? sig_out : 1'bz; assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
wire sig_in = sig; wire sig_in = sig;
localparam IDLE = 3'd0, localparam IDLE = 3'd0,