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Debg compliqué

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Gamenight77
2025-05-12 15:34:02 +02:00
parent 790b85841b
commit 2cb68ce0d1
5 changed files with 38 additions and 30 deletions
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17
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
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@@ -20,16 +20,17 @@ module ultrasonic_fpga #(
reg sig_int, sig_ok;
reg [2:0] state = IDLE;
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
COMPUTE = 3'd5,
DONE = 3'd6,
WAIT_NEXT = 3'd7;
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
COMPUTE = 3'd5,
DONE = 3'd6,
WAIT_NEXT = 3'd7;
reg [2:0] state = IDLE;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm