Debg compliqué

2025-05-12 15:34:02 +02:00
parent 790b85841b
commit 2cb68ce0d1
5 changed files with 38 additions and 30 deletions
--- a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
@@ -65,10 +65,11 @@ module top_uart_ultrason_command (
    reg [1:0] mesure = STOP;

    always @(posedge clk) begin
-        leds [5] <= rx;
+        
        leds [4] <= tx;
        case (rx_state)
            IDLE: begin
+                leds [5] <= 0;
                wr_en <= 0;
                rd_en <= 0;

@@ -81,6 +82,7 @@ module top_uart_ultrason_command (
            end

            READ: begin
+                leds [5] <= 1;
                case (rd_data)
                    8'h01: begin // Start mesure one mesure
                        start <= 1;