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Gamenight77
2025-05-12 15:34:02 +02:00
parent 790b85841b
commit 2cb68ce0d1
5 changed files with 38 additions and 30 deletions
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17
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
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@@ -20,16 +20,17 @@ module ultrasonic_fpga #(
reg sig_int, sig_ok;
reg [2:0] state = IDLE;
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
COMPUTE = 3'd5,
DONE = 3'd6,
WAIT_NEXT = 3'd7;
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
COMPUTE = 3'd5,
DONE = 3'd6,
WAIT_NEXT = 3'd7;
reg [2:0] state = IDLE;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm

2
Semaine_5/UART_ULTRASON_COMMANDS/scripts/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off
echo === Lancement de GTKWave ===
gtkwave runs/uart_rx_fifo.vcd
gtkwave runs/ultrason_commands.vcd

2
Semaine_5/UART_ULTRASON_COMMANDS/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_rx_fifo
set TOP=tb_ultrason_commands
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog

4
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -65,10 +65,11 @@ module top_uart_ultrason_command (
reg [1:0] mesure = STOP;
always @(posedge clk) begin
leds [5] <= rx;
leds [4] <= tx;
case (rx_state)
IDLE: begin
leds [5] <= 0;
wr_en <= 0;
rd_en <= 0;
@@ -81,6 +82,7 @@ module top_uart_ultrason_command (
end
READ: begin
leds [5] <= 1;
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;

41
Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v → Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v
View File

@@ -3,7 +3,7 @@
module tb_ultrason_commands;
reg clk = 0;
always #18.5 clk = ~clk; // ~27 MHz
always #18.5 clk = ~clk; // Génère une clock 27 MHz
wire tx, rx;
wire [5:0] leds;
@@ -15,6 +15,8 @@ module tb_ultrason_commands;
wire [7:0] data_out;
wire rx_received;
reg rd_en = 0; // Lecture FIFO
// === PARAMÈTRES ===
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
@@ -34,19 +36,19 @@ module tb_ultrason_commands;
.signal(ultrason_sig)
);
// === RX : observe ce que le FPGA envoie ===
uart_rx #(
// === RX FIFO pour observer la sortie UART ===
uart_rx_fifo #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uart_rx_inst (
) uart_rx_fifo_inst (
.clk(clk),
.rx_pin(tx), // observe ce que le FPGA envoie
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(1'b1)
.rx_pin(rx), // on observe la sortie du DUT
.rd_en(rd_en),
.rd_data(data_out),
.data_available(rx_received)
);
// === TX : envoie une commande au FPGA ===
// === TX pour injecter une commande UART vers le DUT ===
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
@@ -55,7 +57,7 @@ module tb_ultrason_commands;
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(rx), // vers le FPGA
.tx(tx), // va dans le DUT
.rst_p(1'b0)
);
@@ -66,22 +68,25 @@ module tb_ultrason_commands;
$display("==== Start UART Ultrasonic Test ====");
// Attendre que le tx soit prêt
// Attendre que le TX soit prêt
wait(tx_ready);
#100;
// Envoyer la commande "ONE" (1)
data_in <= 8'd1; // ONE
data_in <= 8'd1;
tx_enable <= 1;
#20;
tx_enable <= 0;
// Attendre la réponse
wait(rx_received);
$display(">> Distance LSB: %d", data_out);
wait(rx_received);
$display(">> Distance MSB: %d", data_out);
// Lire 2 octets de réponse : LSB et MSB de la distance
repeat (2) begin
wait(rx_received);
#10; // Laisse le temps de valider le drapeau
rd_en <= 1; // Lecture de la FIFO
#20;
rd_en <= 0;
$display(">> Distance octet: %d", data_out);
end
$display("==== End UART Ultrasonic Test ====");
#1000;