diff --git a/Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst b/Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst
index 507b900..0c955c8 100644
--- a/Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst
+++ b/Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst
@@ -7,3 +7,15 @@ IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "sig" 73;
IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "leds[0]" 15;
+IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" 16;
+IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[2]" 17;
+IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[3]" 18;
+IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[4]" 19;
+IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[5]" 20;
+IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
\ No newline at end of file
diff --git a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
index 85a7612..358dc3a 100644
--- a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
+++ b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
@@ -2,6 +2,7 @@ module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
+ output reg [5:0] leds
);
@@ -43,7 +44,7 @@ module top_uart_ultrason (
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
- // Activer en continu tant que FIFO pas pleine
+ leds <= distance[7:2];
start <= 1;
case (state)
@@ -63,16 +64,7 @@ module top_uart_ultrason (
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
- state <= WAIT;
- end
-
- WAIT: begin // Code non testé
- if (delay_counter < 1000000) begin
- delay_counter <= delay_counter + 1;
- end else begin
- state <= IDLE;
- delay_counter <= 0;
- end
+ state <= IDLE;
end
endcase
diff --git a/Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py b/Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py
index a80d114..2c43b65 100644
--- a/Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py
+++ b/Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py
@@ -1,9 +1,9 @@
import serial
# === Configuration ===
-PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux)
-BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo
-TIMEOUT = 1 # En secondes
+PORT = 'COM6'
+BAUDRATE = 115200
+TIMEOUT = 1
# === Connexion série ===
ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT)
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
index a67914e..031be59 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
@@ -1,25 +1,24 @@
module fifo #(
- parameter DEPTH = 16,
+ parameter SIZE = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
- output wire[WIDTH-1:0] rd_data,
+ output reg[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
- reg [WIDTH-1:0] fifo[0:DEPTH-1];
+ reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
- assign full = (count == DEPTH);
+ assign full = (count == SIZE);
assign empty = (count == 0);
- assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
@@ -27,15 +26,16 @@
count = 0;
end
- always @(posedge clk) begin
+ always @(posedge clk) begin // IN
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
- wr_ptr <= (wr_ptr + 1) % DEPTH;
+ wr_ptr <= (wr_ptr + 1) % SIZE;
count <= count + 1;
end
- if (rd_en && !empty) begin
- rd_ptr <= (rd_ptr + 1) % DEPTH;
+ if (rd_en && !empty) begin // OUT
+ rd_ptr <= (rd_ptr + 1) % SIZE;
+ rd_data <= fifo[rd_ptr];
count <= count - 1;
end
end
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/rxuartlite.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/rxuartlite.v
new file mode 100644
index 0000000..a527848
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/rxuartlite.v
@@ -0,0 +1,796 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: rxuartlite.v
+// {{{
+// Project: wbuart32, a full featured UART with simulator
+//
+// Purpose: Receive and decode inputs from a single UART line.
+//
+//
+// To interface with this module, connect it to your system clock,
+// and a UART input. Set the parameter to the number of clocks per
+// baud. When data becomes available, the o_wr line will be asserted
+// for one clock cycle.
+//
+// This interface only handles 8N1 serial port communications. It does
+// not handle the break, parity, or frame error conditions.
+//
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Copyright (C) 2015-2024, Gisselquist Technology, LLC
+// {{{
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// for a copy.
+// }}}
+// License: GPL, v3, as defined and found on www.gnu.org,
+// {{{
+// http://www.gnu.org/licenses/gpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+`default_nettype none
+// }}}
+module rxuartlite #(
+ // {{{
+ parameter TIMER_BITS = 10,
+`ifdef FORMAL
+ parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
+`else
+ parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
+`endif
+ localparam TB = TIMER_BITS,
+ //
+ localparam [3:0] RXUL_BIT_ZERO = 4'h0,
+ // Verilator lint_off UNUSED
+ // These are used by the formal solver
+ localparam [3:0] RXUL_BIT_ONE = 4'h1,
+ localparam [3:0] RXUL_BIT_TWO = 4'h2,
+ localparam [3:0] RXUL_BIT_THREE = 4'h3,
+ localparam [3:0] RXUL_BIT_FOUR = 4'h4,
+ localparam [3:0] RXUL_BIT_FIVE = 4'h5,
+ localparam [3:0] RXUL_BIT_SIX = 4'h6,
+ localparam [3:0] RXUL_BIT_SEVEN = 4'h7,
+ // Verilator lint_on UNUSED
+ localparam [3:0] RXUL_STOP = 4'h8,
+ localparam [3:0] RXUL_WAIT = 4'h9,
+ localparam [3:0] RXUL_IDLE = 4'hf
+ // }}}
+ ) (
+ // {{{
+ input wire i_clk, i_reset,
+ input wire i_uart_rx,
+ output reg o_wr,
+ output reg [7:0] o_data
+ // }}}
+ );
+
+ // Signal/register declarations
+ // {{{
+ wire [(TB-1):0] half_baud;
+ reg [3:0] state;
+
+ assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] };
+ reg [(TB-1):0] baud_counter;
+ reg zero_baud_counter;
+
+ reg q_uart, qq_uart, ck_uart;
+ reg [(TB-1):0] chg_counter;
+ reg half_baud_time;
+ reg [7:0] data_reg;
+ // }}}
+
+ // ck_uart
+ // {{{
+ // Since this is an asynchronous receiver, we need to register our
+ // input a couple of clocks over to avoid any problems with
+ // metastability. We do that here, and then ignore all but the
+ // ck_uart wire.
+ initial q_uart = 1'b1;
+ initial qq_uart = 1'b1;
+ initial ck_uart = 1'b1;
+ always @(posedge i_clk)
+ if (i_reset)
+ { ck_uart, qq_uart, q_uart } <= 3'b111;
+ else
+ { ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx };
+ // }}}
+
+ // chg_counter
+ // {{{
+ // Keep track of the number of clocks since the last change.
+ //
+ // This is used to determine if we are in either a break or an idle
+ // condition, as discussed further below.
+ initial chg_counter = {(TB){1'b1}};
+ always @(posedge i_clk)
+ if (i_reset)
+ chg_counter <= {(TB){1'b1}};
+ else if (qq_uart != ck_uart)
+ chg_counter <= 0;
+ else if (chg_counter != { (TB){1'b1} })
+ chg_counter <= chg_counter + 1;
+ // }}}
+
+ // half_baud_time
+ // {{{
+ // Are we in the middle of a baud iterval? Specifically, are we
+ // in the middle of a start bit? Set this to high if so. We'll use
+ // this within our state machine to transition out of the IDLE
+ // state.
+ initial half_baud_time = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ half_baud_time <= 0;
+ else
+ half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1);
+ // }}}
+
+ // state
+ // {{{
+ initial state = RXUL_IDLE;
+ always @(posedge i_clk)
+ if (i_reset)
+ begin
+ state <= RXUL_IDLE;
+ end else if (state == RXUL_IDLE)
+ begin // Idle state, independent of baud counter
+ // {{{
+ // By default, just stay in the IDLE state
+ state <= RXUL_IDLE;
+ if ((!ck_uart)&&(half_baud_time))
+ // UNLESS: We are in the center of a valid
+ // start bit
+ state <= RXUL_BIT_ZERO;
+ // }}}
+ end else if ((state >= RXUL_WAIT)&&(ck_uart))
+ state <= RXUL_IDLE;
+ else if (zero_baud_counter)
+ begin
+ // {{{
+ if (state <= RXUL_STOP)
+ // Data arrives least significant bit first.
+ // By the time this is clocked in, it's what
+ // you'll have.
+ state <= state + 1;
+ // }}}
+ end
+ // }}}
+
+ // data_reg
+ // {{{
+ // Data bit capture logic.
+ //
+ // This is drastically simplified from the state machine above, based
+ // upon: 1) it doesn't matter what it is until the end of a captured
+ // byte, and 2) the data register will flush itself of any invalid
+ // data in all other cases. Hence, let's keep it real simple.
+ always @(posedge i_clk)
+ if ((zero_baud_counter)&&(state != RXUL_STOP))
+ data_reg <= { qq_uart, data_reg[7:1] };
+ // }}}
+
+ // o_wr, o_data
+ // {{{
+ // Our data bit logic doesn't need nearly the complexity of all that
+ // work above. Indeed, we only need to know if we are at the end of
+ // a stop bit, in which case we copy the data_reg into our output
+ // data register, o_data, and tell others (for one clock) that data is
+ // available.
+ //
+ initial o_wr = 1'b0;
+ initial o_data = 8'h00;
+ always @(posedge i_clk)
+ if (i_reset)
+ begin
+ o_wr <= 1'b0;
+ o_data <= 8'h00;
+ end else if ((zero_baud_counter)&&(state == RXUL_STOP)&&(ck_uart))
+ begin
+ o_wr <= 1'b1;
+ o_data <= data_reg;
+ end else
+ o_wr <= 1'b0;
+ // }}}
+
+ // baud_counter -- The baud counter
+ // {{{
+ // This is used as a "clock divider" if you will, but the clock needs
+ // to be reset before any byte can be decoded. In all other respects,
+ // we set ourselves up for CLOCKS_PER_BAUD counts between baud
+ // intervals.
+ initial baud_counter = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ baud_counter <= 0;
+ else if (((state==RXUL_IDLE))&&(!ck_uart)&&(half_baud_time))
+ baud_counter <= CLOCKS_PER_BAUD-1'b1;
+ else if (state == RXUL_WAIT)
+ baud_counter <= 0;
+ else if ((zero_baud_counter)&&(state < RXUL_STOP))
+ baud_counter <= CLOCKS_PER_BAUD-1'b1;
+ else if (!zero_baud_counter)
+ baud_counter <= baud_counter-1'b1;
+ // }}}
+
+ // zero_baud_counter
+ // {{{
+ // Rather than testing whether or not (baud_counter == 0) within our
+ // (already too complicated) state transition tables, we use
+ // zero_baud_counter to pre-charge that test on the clock
+ // before--cleaning up some otherwise difficult timing dependencies.
+ initial zero_baud_counter = 1'b1;
+ always @(posedge i_clk)
+ if (i_reset)
+ zero_baud_counter <= 1'b1;
+ else if ((state == RXUL_IDLE)&&(!ck_uart)&&(half_baud_time))
+ zero_baud_counter <= 1'b0;
+ else if (state == RXUL_WAIT)
+ zero_baud_counter <= 1'b1;
+ else if ((zero_baud_counter)&&(state < RXUL_STOP))
+ zero_baud_counter <= 1'b0;
+ else if (baud_counter == 1)
+ zero_baud_counter <= 1'b1;
+ // }}}
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+// Formal properties
+// {{{
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+ // Declarations
+ // {{{
+`ifdef FORMAL
+`define FORMAL_VERILATOR
+`else
+`ifdef VERILATOR
+`define FORMAL_VERILATOR
+`endif
+`endif
+
+`ifdef FORMAL
+ localparam F_CKRES = 10;
+
+ (* anyseq *) wire f_tx_start;
+ (* anyconst *) wire [(F_CKRES-1):0] f_tx_step;
+ (* gclk *) wire gbl_clk;
+ reg f_tx_zclk;
+ reg [(TB-1):0] f_tx_timer;
+ wire [7:0] f_rx_newdata;
+ reg [TB-1:0] f_tx_baud;
+ wire f_tx_zbaud;
+
+ wire [(TB-1):0] f_max_baud_difference;
+ reg [(TB-1):0] f_baud_difference;
+ reg [(TB+3):0] f_tx_count, f_rx_count;
+ (* anyseq *) wire [7:0] f_tx_data;
+
+ wire f_txclk;
+ reg [1:0] f_rx_clock;
+ reg [(F_CKRES-1):0] f_tx_clock;
+ reg f_past_valid, f_past_valid_tx;
+
+ reg [9:0] f_tx_reg;
+ reg f_tx_busy;
+
+ // }}}
+
+ initial f_past_valid = 1'b0;
+ always @(posedge i_clk)
+ f_past_valid <= 1'b1;
+
+ initial f_rx_clock = 3'h0;
+ always @(posedge gbl_clk)
+ f_rx_clock <= f_rx_clock + 1'b1;
+
+ always @(*)
+ assume(i_clk == f_rx_clock[1]);
+
+ always @(posedge gbl_clk)
+ if (!$rose(i_clk))
+ assume(!$fell(i_reset));
+
+
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Assume a transmitted signal
+ // {{{
+ ////////////////////////////////////////////////////////////////////////
+ //
+ //
+
+ // First, calculate the transmit clock
+ localparam [(F_CKRES-1):0] F_MIDSTEP = { 2'b01, {(F_CKRES-2){1'b0}} };
+ //
+ // Need to allow us to slip by half a baud clock over 10 baud intervals
+ //
+ // (F_STEP / (2^F_CKRES)) * (CLOCKS_PER_BAUD)*10 < CLOCKS_PER_BAUD/2
+ // F_STEP * 2 * 10 < 2^F_CKRES
+ localparam [(F_CKRES-1):0] F_HALFSTEP= F_MIDSTEP/32;
+ localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1;
+ localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1;
+
+ initial assert(F_MINSTEP <= F_MIDSTEP);
+ initial assert(F_MIDSTEP <= F_MAXSTEP);
+
+ // assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));
+ //
+ //
+ always @(*) assume((f_tx_step == F_MINSTEP)
+ ||(f_tx_step == F_MIDSTEP)
+ ||(f_tx_step == F_MAXSTEP));
+
+ always @(posedge gbl_clk)
+ f_tx_clock <= f_tx_clock + f_tx_step;
+
+ assign f_txclk = f_tx_clock[F_CKRES-1];
+ //
+ initial f_past_valid_tx = 1'b0;
+ always @(posedge f_txclk)
+ f_past_valid_tx <= 1'b1;
+
+ initial assume(i_uart_rx);
+
+ always @(*)
+ if (i_reset)
+ assume(i_uart_rx);
+
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // The simulated timing generator
+
+ always @(*)
+ if (i_reset)
+ assume(!f_tx_busy);
+
+ always @(*)
+ if (f_tx_busy || i_reset)
+ assume(!f_tx_start);
+
+ always @(*)
+ if (i_reset)
+ assume(f_tx_baud == CLOCKS_PER_BAUD-1);
+
+ initial f_tx_baud = 0;
+ always @(posedge f_txclk)
+ if (f_tx_zbaud && (f_tx_busy || f_tx_start))
+ f_tx_baud <= CLOCKS_PER_BAUD-1;
+ else if (!f_tx_zbaud)
+ f_tx_baud <= f_tx_baud - 1;
+
+ always @(*)
+ assert(f_tx_baud < CLOCKS_PER_BAUD);
+
+ always @(*)
+ if (!f_tx_busy)
+ assert(f_tx_baud == 0);
+
+ assign f_tx_zbaud = (f_tx_baud == 0);
+
+ // But only if we aren't busy
+ initial assume(f_tx_data == 0);
+ always @(posedge f_txclk)
+ if ((!f_tx_zbaud)||(f_tx_busy)||(!f_tx_start))
+ assume(f_tx_data == $past(f_tx_data));
+
+ // Force the data to change on a clock only
+ always @(posedge gbl_clk)
+ if ((f_past_valid)&&(!$rose(f_txclk)))
+ assume($stable(f_tx_data));
+ else if (f_tx_busy)
+ assume($stable(f_tx_data));
+
+ //
+ always @(posedge gbl_clk)
+ if ((!f_past_valid)||(!$rose(f_txclk)))
+ begin
+ assume($stable(f_tx_start));
+ assume($stable(f_tx_data));
+ end
+
+ //
+ //
+ //
+
+ // Here's the transmitter itself (roughly)
+ initial f_tx_busy = 1'b0;
+ initial f_tx_reg = 0;
+ always @(posedge f_txclk)
+ if (!f_tx_zbaud)
+ begin
+ assert(f_tx_busy);
+ end else begin
+ f_tx_reg <= { 1'b0, f_tx_reg[9:1] };
+ if (f_tx_start)
+ f_tx_reg <= { 1'b1, f_tx_data, 1'b0 };
+ end
+
+ // Create a busy flag that we'll use
+ always @(*)
+ if (!f_tx_zbaud)
+ f_tx_busy <= 1'b1;
+ else if (|f_tx_reg)
+ f_tx_busy <= 1'b1;
+ else
+ f_tx_busy <= 1'b0;
+
+ //
+ // Tie the TX register to the TX data
+ always @(posedge f_txclk)
+ if (f_tx_reg[9])
+ begin
+ assert(f_tx_reg[8:0] == { f_tx_data, 1'b0 });
+ end else if (f_tx_reg[8])
+ begin
+ assert(f_tx_reg[7:0] == f_tx_data[7:0] );
+ end else if (f_tx_reg[7])
+ begin
+ assert(f_tx_reg[6:0] == f_tx_data[7:1] );
+ end else if (f_tx_reg[6])
+ begin
+ assert(f_tx_reg[5:0] == f_tx_data[7:2] );
+ end else if (f_tx_reg[5])
+ begin
+ assert(f_tx_reg[4:0] == f_tx_data[7:3] );
+ end else if (f_tx_reg[4])
+ begin
+ assert(f_tx_reg[3:0] == f_tx_data[7:4] );
+ end else if (f_tx_reg[3])
+ begin
+ assert(f_tx_reg[2:0] == f_tx_data[7:5] );
+ end else if (f_tx_reg[2])
+ begin
+ assert(f_tx_reg[1:0] == f_tx_data[7:6] );
+ end else if (f_tx_reg[1])
+ begin
+ assert(f_tx_reg[0] == f_tx_data[7]);
+ end
+
+ // Our counter since we start
+ initial f_tx_count = 0;
+ always @(posedge f_txclk)
+ if (!f_tx_busy)
+ f_tx_count <= 0;
+ else
+ f_tx_count <= f_tx_count + 1'b1;
+
+ always @(*)
+ if (f_tx_reg == 10'h0)
+ assume(i_uart_rx);
+ else
+ assume(i_uart_rx == f_tx_reg[0]);
+
+ //
+ // Make sure the absolute transmit clock timer matches our state
+ //
+ always @(posedge f_txclk)
+ if (!f_tx_busy)
+ begin
+ if ((!f_past_valid_tx)||(!$past(f_tx_busy)))
+ assert(f_tx_count == 0);
+ end else if (f_tx_reg[9])
+ begin
+ assert(f_tx_count ==
+ CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[8])
+ begin
+ assert(f_tx_count ==
+ 2 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[7])
+ begin
+ assert(f_tx_count ==
+ 3 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[6])
+ begin
+ assert(f_tx_count ==
+ 4 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[5])
+ begin
+ assert(f_tx_count ==
+ 5 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[4])
+ begin
+ assert(f_tx_count ==
+ 6 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[3])
+ begin
+ assert(f_tx_count ==
+ 7 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[2])
+ begin
+ assert(f_tx_count ==
+ 8 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[1])
+ begin
+ assert(f_tx_count ==
+ 9 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else if (f_tx_reg[0])
+ begin
+ assert(f_tx_count ==
+ 10 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end else begin
+ assert(f_tx_count ==
+ 11 * CLOCKS_PER_BAUD -1 -f_tx_baud);
+ end
+
+ // }}}
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Receiver
+ // {{{
+ ////////////////////////////////////////////////////////////////////////
+ //
+ //
+ // Count RX clocks since the start of the first stop bit, measured in
+ // rx clocks
+ initial f_rx_count = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ f_rx_count <= 0;
+ else if (state == RXUL_IDLE)
+ f_rx_count <= (!ck_uart) ? (chg_counter+2) : 0;
+ else
+ f_rx_count <= f_rx_count + 1'b1;
+
+ always @(posedge i_clk)
+ case(state)
+ 0: assert(f_rx_count == half_baud + (CLOCKS_PER_BAUD-baud_counter));
+ 1: assert(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 2: assert(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 3: assert(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 4: assert(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 5: assert(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 6: assert(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 7: assert(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD
+ - baud_counter);
+ 8: assert((f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD
+ - baud_counter)
+ ||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD
+ - baud_counter));
+ 9: begin end
+ 4'hf: begin end
+ default:
+ assert(1'b0);
+ endcase
+
+ always @(*)
+ assert( ((!zero_baud_counter)
+ &&(state == RXUL_IDLE)
+ &&(baud_counter == 0))
+ ||((zero_baud_counter)&&(baud_counter == 0))
+ ||((!zero_baud_counter)&&(baud_counter != 0)));
+
+ always @(posedge i_clk)
+ if (!f_past_valid)
+ assert((state == RXUL_IDLE)&&(baud_counter == 0)
+ &&(zero_baud_counter));
+
+ always @(*)
+ begin
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h2);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h4);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h5);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h6);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h9);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'ha);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hb);
+ assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hd);
+ end
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&($past(state) >= RXUL_WAIT)&&($past(ck_uart)))
+ assert(state == RXUL_IDLE);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&($past(state) >= RXUL_WAIT)
+ &&(($past(state) != RXUL_IDLE)||(state == RXUL_IDLE)))
+ assert(zero_baud_counter);
+
+ // Calculate an absolute value of the difference between the two baud
+ // clocks
+ always @(posedge i_clk)
+ if (f_past_valid && !$past(i_reset)
+ && $past(state)==RXUL_IDLE &&(state == RXUL_IDLE))
+ begin
+ assert(($past(ck_uart))
+ ||(chg_counter <=
+ { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] }));
+ end
+
+ always @(posedge f_txclk)
+ if (!f_past_valid_tx)
+ assert((state == RXUL_IDLE)&&(baud_counter == 0)
+ &&(zero_baud_counter)&&(!f_tx_busy));
+
+ wire [(TB+3):0] f_tx_count_two_clocks_ago;
+ assign f_tx_count_two_clocks_ago = f_tx_count - 2;
+ always @(*)
+ if (f_tx_count >= f_rx_count + 2)
+ f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count;
+ else
+ f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago;
+
+ localparam F_SYNC_DLY = 8;
+
+ reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference;
+ reg [F_CKRES-1:0] ck_tx_clock;
+ reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock;
+ reg [TB+3:0] ck_tx_count;
+ reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count;
+ initial q_tx_count = 0;
+ initial ck_tx_count = 0;
+ initial q_tx_clock = 0;
+ initial ck_tx_clock = 0;
+ always @(posedge gbl_clk)
+ if (!f_past_valid || i_reset)
+ { ck_tx_clock, q_tx_clock } <= 0;
+ else
+ { ck_tx_clock, q_tx_clock } <= { q_tx_clock, f_tx_clock };
+ always @(posedge gbl_clk)
+ if (!f_past_valid || i_reset)
+ { ck_tx_count, q_tx_count } <= 0;
+ else
+ { ck_tx_count, q_tx_count } <= { q_tx_count, f_tx_count };
+
+
+ reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time;
+ always @(*)
+ f_ck_tx_time = { ck_tx_count, !ck_tx_clock[F_CKRES-1],
+ ck_tx_clock[F_CKRES-2:0] };
+ always @(*)
+ f_rx_time = { f_rx_count, !f_rx_clock[1], f_rx_clock[0],
+ {(F_CKRES-2){1'b0}} };
+
+ reg [TB+4+F_CKRES-1:0] f_signed_difference;
+ always @(*)
+ f_signed_difference = f_ck_tx_time - f_rx_time;
+
+ always @(*)
+ if (f_signed_difference[TB+4+F_CKRES-1])
+ f_sub_baud_difference = -f_signed_difference;
+ else
+ f_sub_baud_difference = f_signed_difference;
+
+ always @(posedge gbl_clk)
+ if (state == RXUL_WAIT)
+ assert((!f_tx_busy)||(f_tx_reg[9:1] == 0));
+
+ always @(posedge gbl_clk)
+ if (f_past_valid && !$past(i_reset))
+ begin
+ if (state == RXUL_IDLE)
+ begin
+ assert((!f_tx_busy)||(f_tx_reg[9])||(f_tx_reg[9:1]==0));
+ if (ck_uart)
+ assert((f_tx_reg[9:1]==0)||(f_tx_count < (3 + CLOCKS_PER_BAUD/2)));
+ end else if (state == 0)
+ begin
+ assert(f_sub_baud_difference
+ <= 2 * ((CLOCKS_PER_BAUD< 6))
+ // assert(i_uart_rx == ck_uart);
+
+ // Make sure the data register matches
+ always @(posedge i_clk)
+ case(state)
+ 4'h0: assert(!data_reg[7]);
+ 4'h1: assert((data_reg[7] == $past(f_tx_data[0]))&&(!data_reg[6]));
+ 4'h2: assert(data_reg[7:6] == $past(f_tx_data[1:0]));
+ 4'h3: assert(data_reg[7:5] == $past(f_tx_data[2:0]));
+ 4'h4: assert(data_reg[7:4] == $past(f_tx_data[3:0]));
+ 4'h5: assert(data_reg[7:3] == $past(f_tx_data[4:0]));
+ 4'h6: assert(data_reg[7:2] == $past(f_tx_data[5:0]));
+ 4'h7: assert(data_reg[7:1] == $past(f_tx_data[6:0]));
+ 4'h8: assert(data_reg[7:0] == $past(f_tx_data[7:0]));
+ endcase
+ // }}}
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Cover properties
+ // {{{
+ ////////////////////////////////////////////////////////////////////////
+ //
+ always @(posedge i_clk)
+ cover(o_wr); // Step 626, takes about 20mins
+
+ always @(posedge i_clk)
+ if (!i_reset && f_past_valid && !$past(i_reset))
+ begin
+ cover(!ck_uart);
+ cover((f_past_valid)&&($rose(ck_uart))); // 82
+ cover((zero_baud_counter)&&(state == RXUL_BIT_ZERO)); // 110
+ cover((zero_baud_counter)&&(state == RXUL_BIT_ONE)); // 174
+ cover((zero_baud_counter)&&(state == RXUL_BIT_TWO)); // 238
+ cover((zero_baud_counter)&&(state == RXUL_BIT_THREE));// 302
+ cover((zero_baud_counter)&&(state == RXUL_BIT_FOUR)); // 366
+ cover((zero_baud_counter)&&(state == RXUL_BIT_FIVE)); // 430
+ cover((zero_baud_counter)&&(state == RXUL_BIT_SIX)); // 494
+ cover((zero_baud_counter)&&(state == RXUL_BIT_SEVEN));// 558
+ cover((zero_baud_counter)&&(state == RXUL_STOP)); // 622
+ cover((zero_baud_counter)&&(state == RXUL_WAIT)); // 626
+ end
+`endif
+ // }}}
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Properties to test via Verilator *and* formal
+ // {{{
+ ////////////////////////////////////////////////////////////////////////
+ //
+`ifdef FORMAL_VERILATOR
+ // FORMAL properties which can be tested via Verilator as well as
+ // Yosys FORMAL
+ always @(*)
+ assert((state == 4'hf)||(state <= RXUL_WAIT));
+ always @(*)
+ assert(zero_baud_counter == (baud_counter == 0)? 1'b1:1'b0);
+ always @(*)
+ assert(baud_counter <= CLOCKS_PER_BAUD-1'b1);
+ // }}}
+`endif
+// }}}
+endmodule
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
new file mode 100644
index 0000000..c9e8625
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
@@ -0,0 +1,64 @@
+module uart_rx_fifo #(
+ parameter CLK_FREQ = 27_000_000,
+ parameter BAUD_RATE = 115200,
+ parameter FIFO_SIZE = 8
+)(
+ input clk,
+ input rd_en,
+ output reg [7:0] rd_data,
+ input rx_pin,
+ output data_available
+);
+
+ // UART RX wires
+ wire [7:0] rx_data;
+ wire rx_received;
+
+ // FIFO control
+ reg wr_en;
+ wire fifo_empty;
+ wire fifo_full;
+ wire [7:0] fifo_rd_data;
+
+ // UART Receiver instance
+ rxuartlite uart_rx_inst (
+ .i_clk(clk),
+ .i_reset(1'b0),
+ .i_uart_rx(rx_pin),
+ .o_wr(rx_received),
+ .o_data(rx_data)
+ );
+
+ // FIFO instance
+ fifo #(
+ .WIDTH(8),
+ .SIZE(FIFO_SIZE)
+ ) fifo_inst (
+ .clk(clk),
+ .wr_en(wr_en),
+ .wr_data(rx_data),
+ .rd_en(rd_en),
+ .rd_data(fifo_rd_data),
+ .empty(fifo_empty),
+ .full(fifo_full)
+ );
+
+ assign data_available = ~fifo_empty;
+
+ // Enregistrement explicite des données lues pour stabilité
+ always @(posedge clk) begin
+ if (rd_en && !fifo_empty) begin
+ rd_data <= fifo_rd_data;
+ end
+ end
+
+ // Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
+ always @(posedge clk) begin
+ if (rx_received && !fifo_full) begin
+ wr_en <= 1'b1;
+ end else begin
+ wr_en <= 1'b0;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
index 80ebb84..d09ecc3 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
@@ -1,7 +1,7 @@
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
- parameter FIFO_DEPTH = 8
+ parameter FIFO_SIZE = 8
)(
input clk,
input wr_en,
@@ -32,7 +32,7 @@ module uart_tx_fifo #(
// FIFO instantiation
fifo #(
.WIDTH(8),
- .DEPTH(FIFO_DEPTH)
+ .SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_sensor.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_sensor.v
new file mode 100644
index 0000000..ea560c0
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_sensor.v
@@ -0,0 +1,95 @@
+module ultrasonic_sensor( // Simulation of an ultrasonic sensor
+ input wire clk,
+ inout wire signal // Signal from the ultrasonic sensor
+);
+ parameter integer CLK_FREQ = 27_000_000;
+
+ reg [2:0] state = 3'd0; // State of the FSM
+ reg [2:0] next_state;
+ reg sig_dir; // 1: output, 0: input
+ reg [15:0] trig_counter = 0; // Counter for the trigger pulse
+ reg [31:0] echo_counter = 0; // Echo signal
+ reg valid_trig = 0; // Valid trigger signal
+
+ reg echo_sended = 0; // Flag to indicate if echo has been sent
+
+ reg signal_out = 0;
+ assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
+
+ localparam S_WAIT_TRIG = 3'd0,
+ S_MEASURE_TRIG = 3'd1,
+ S_SEND_ECHO = 3'd2;
+
+ localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
+
+ always @(*) begin
+ case (state)
+ S_WAIT_TRIG: begin
+ sig_dir = 0;
+ if (signal == 1) begin
+ next_state = S_MEASURE_TRIG;
+ end else begin
+ next_state = S_WAIT_TRIG;
+ end
+ end
+
+ S_MEASURE_TRIG: begin
+ sig_dir = 0;
+ if (valid_trig)begin
+ next_state = S_SEND_ECHO;
+ end
+ end
+
+ S_SEND_ECHO: begin
+ sig_dir = 1; // Mettre en sortie
+
+ if (echo_sended) begin
+ echo_sended = 0; // Reset flag
+ next_state = S_WAIT_TRIG;
+ end else begin
+ next_state = S_SEND_ECHO;
+ end
+ end
+
+ default: begin
+ sig_dir = 0;
+ next_state = S_WAIT_TRIG;
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ state <= next_state;
+ end
+
+ always @(posedge clk) begin
+ if (state == S_MEASURE_TRIG) begin
+ if (signal == 1) begin
+ trig_counter <= trig_counter + 1;
+ end else begin
+ if (trig_counter >= TRIG_PULSE_CYCLES-20) begin
+ valid_trig <= 1;
+ end else begin
+ valid_trig <= 0;
+ end
+ end
+ end
+ end
+
+ reg [15:0] echo_delay_counter;
+
+ always @(posedge clk) begin
+ if (state == S_SEND_ECHO) begin
+ if (echo_delay_counter == 5800) begin //
+ signal_out <= 0;
+ echo_sended <= 1;
+ end else begin
+ signal_out <= 1;
+ echo_delay_counter <= echo_delay_counter + 1;
+ end
+ end else begin
+ echo_delay_counter <= 0;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst b/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst
deleted file mode 100644
index 507b900..0000000
--- a/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst
+++ /dev/null
@@ -1,9 +0,0 @@
-IO_LOC "tx" 69;
-IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-
-IO_LOC "clk" 4;
-IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-
-IO_LOC "sig" 73;
-IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason_command.cst b/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason_command.cst
new file mode 100644
index 0000000..110a02b
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason_command.cst
@@ -0,0 +1,24 @@
+IO_LOC "tx" 69;
+IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "rx" 70;
+IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "clk" 4;
+IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "ultrason_sig" 73;
+IO_PORT "ultrason_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+IO_LOC "leds[0]" 15;
+IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" 16;
+IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[2]" 17;
+IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[3]" 18;
+IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[4]" 19;
+IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[5]" 20;
+IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat
index c4a0fcf..89520d5 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat
@@ -7,7 +7,7 @@ cd /d %~dp0\..
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
-set TOP=top_uart_ultrason
+set TOP=top_uart_ultrason_command
set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json
@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
-yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v
deleted file mode 100644
index 85a7612..0000000
--- a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v
+++ /dev/null
@@ -1,81 +0,0 @@
-module top_uart_ultrason (
- input wire clk, // 27 MHz
- output wire tx,
- inout wire sig, // Capteur ultrason
-);
-
-
- // === UART TX WIRE ===
- reg [7:0] wr_data;
- reg wr_en;
- wire tx_fifo_full;
-
- // === UART TX FIFO ===
- uart_tx_fifo uart_tx_inst (
- .clk(clk),
- .wr_en(wr_en),
- .wr_data(wr_data),
- .fifo_full(tx_fifo_full),
- .tx_pin(tx)
- );
-
- // === Ultrasonic ===
- reg start = 0;
- wire ultrasonic_busy;
- wire [15:0] distance;
- wire done;
-
- ultrasonic_fpga #(
- .CLK_FREQ(27_000_000)
- ) ultrasonic_inst (
- .clk(clk),
- .start(start),
- .sig(sig),
- .distance(distance),
- .busy(ultrasonic_busy),
- .done(done)
- );
-
- // === FSM ===
- localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3;
- reg [1:0] state = IDLE;
-
- reg [8:0] delay_counter = 0;
-
- always @(posedge clk) begin
- // Activer en continu tant que FIFO pas pleine
- start <= 1;
-
- case (state)
- IDLE: begin
- wr_en <= 0;
- if (done) begin
- state <= SEND_LOW;
- wr_en <= 1;
- end
- end
-
- SEND_LOW: begin
- wr_en <= 1;
- wr_data <= distance[7:0]; // Octet LSB
- state <= SEND_HIGH;
- end
-
- SEND_HIGH: begin
- wr_data <= distance[15:8]; // Octet MSB
- state <= WAIT;
- end
-
- WAIT: begin // Code non testé
- if (delay_counter < 1000000) begin
- delay_counter <= delay_counter + 1;
- end else begin
- state <= IDLE;
- delay_counter <= 0;
- end
- end
-
- endcase
- end
-
-endmodule
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
new file mode 100644
index 0000000..c7bd6ec
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
@@ -0,0 +1,175 @@
+module top_uart_ultrason_command (
+ input wire clk, // 27 MHz
+ output wire tx,
+ input wire rx,
+ inout wire ultrason_sig, // Capteur ultrason
+ output reg [5:0] leds
+);
+
+ // === UART RX WIRE ===
+ wire [7:0] rd_data;
+ reg rd_en = 0;
+ wire data_available;
+
+ // RX FIFO Instance
+ uart_rx_fifo uart_rx_inst (
+ .clk(clk),
+ .rx_pin(rx),
+ .rd_data(rd_data),
+ .rd_en(rd_en),
+ .data_available(data_available)
+ );
+
+ // === UART TX WIRE ===
+ reg [7:0] wr_data;
+ reg wr_en;
+ wire tx_fifo_full;
+
+ // === UART TX FIFO ===
+ uart_tx_fifo uart_tx_inst (
+ .clk(clk),
+ .wr_en(wr_en),
+ .wr_data(wr_data),
+ .fifo_full(tx_fifo_full),
+ .tx_pin(tx)
+ );
+
+ // === Ultrasonic ===
+ reg start = 0;
+ wire ultrasonic_busy;
+ wire [15:0] distance;
+ wire done;
+
+ ultrasonic_fpga #(
+ .CLK_FREQ(27_000_000)
+ ) ultrasonic_inst (
+ .clk(clk),
+ .start(start),
+ .sig(ultrason_sig),
+ .distance(distance),
+ .busy(ultrasonic_busy),
+ .done(done)
+ );
+
+ // === FSM ===
+ localparam IDLE = 0, READ = 1;
+ localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
+
+ reg [1:0] rx_state = IDLE;
+ reg [1:0] command = 0;
+
+ reg [8:0] delay_counter = 0;
+
+ localparam MESURE = 1, SEND_LOW = 2, SEND_HIGH = 3, WAIT = 4;
+ reg [1:0] tx_state = MESURE;
+ reg [1:0] mesure = STOP;
+
+ always @(posedge clk) begin
+ leds [5] <= rx;
+ leds [4] <= tx;
+ case (rx_state)
+ IDLE: begin
+ wr_en <= 0;
+ rd_en <= 0;
+
+ if (data_available && !tx_fifo_full) begin
+ rd_en <= 1'b1;
+ rx_state <= READ;
+ end else begin
+ rx_state <= IDLE;
+ end
+ end
+
+ READ: begin
+ case (rd_data)
+ 8'h01: begin // Start mesure one mesure
+ start <= 1;
+ mesure <= ONE;
+ rx_state <= IDLE;
+ end
+
+ 8'h02: begin // Start mesure continuous mesure
+ start <= 1;
+ mesure <= CONTINUOUS;
+ rx_state <= IDLE;
+ end
+
+ 8'h03: begin // Stop mesure
+ start <= 0;
+ mesure <= STOP;
+ rx_state <= IDLE;
+ end
+
+ default: begin
+ mesure <= STOP;
+ rx_state <= IDLE;
+ end
+ endcase
+ end
+
+ endcase
+ end
+
+ // Mesure block
+ always @(posedge clk) begin
+ leds <= mesure[1:0];
+ case (tx_state)
+ MESURE: begin
+ case (mesure)
+ STOP: begin // Stop mesure
+ start <= 0;
+ end
+
+ ONE: begin // One mesure
+ start <= 1;
+ if (done) begin
+ tx_state <= SEND_LOW;
+ wr_en <= 1;
+ end else begin
+ tx_state <= MESURE;
+ mesure <= STOP;
+ end
+ end
+
+ CONTINUOUS: begin // Continuous mesure
+ start <= 1;
+ if (done) begin
+ tx_state <= SEND_LOW;
+ wr_en <= 1;
+ end else begin
+ tx_state <= IDLE;
+ end
+ end
+
+ default:
+ start <= 0;
+ endcase
+ end
+
+ SEND_LOW: begin
+ wr_en <= 1;
+ wr_data <= distance[7:0]; // Octet LSB
+ tx_state <= SEND_HIGH;
+ end
+
+ SEND_HIGH: begin
+ wr_data <= distance[15:8]; // Octet MSB
+ tx_state <= WAIT;
+ end
+
+ WAIT: begin // Code non testé
+ if (delay_counter < 1000000) begin
+ delay_counter <= delay_counter + 1;
+ end else begin
+ tx_state <= MESURE;
+ delay_counter <= 0;
+ end
+ wr_en <= 0;
+ end
+
+ default:
+ tx_state <= MESURE;
+ endcase
+ end
+
+endmodule
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py
deleted file mode 100644
index a80d114..0000000
--- a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py
+++ /dev/null
@@ -1,21 +0,0 @@
-import serial
-
-# === Configuration ===
-PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux)
-BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo
-TIMEOUT = 1 # En secondes
-
-# === Connexion série ===
-ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT)
-print(f"Ouvert sur {PORT} à {BAUDRATE} bauds.")
-
-try:
- while True:
- data = ser.read(1) # Lire 1 octet
- if data:
- value = int.from_bytes(data, byteorder='little')
- print(f"Distance mesurée : {value} cm")
-except KeyboardInterrupt:
- print("\nArrêté par l'utilisateur.")
-finally:
- ser.close()
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/ultrason_command.py b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/ultrason_command.py
new file mode 100644
index 0000000..2bdab1e
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/ultrason_command.py
@@ -0,0 +1,68 @@
+import serial
+import time
+import struct
+
+# === Paramètres de communication ===
+SERIAL_PORT = "COM6" # Modifie selon ton système, ex. "/dev/ttyUSB0" sur Linux
+BAUDRATE = 115200 # Change si différent
+TIMEOUT = 2 # secondes
+
+# === Commandes (doivent correspondre aux valeurs Verilog) ===
+CMD_STOP = 3
+CMD_ONE = 1
+CMD_CONTINUOUS = 2
+
+def send_command(ser, command):
+ """Envoie une commande au FPGA"""
+ ser.write(bytes([command]))
+
+def read_distance(ser):
+ """Lit 2 octets et les convertit en distance (int16)"""
+ data = ser.read(2)
+ if len(data) != 2:
+ return None
+ # Interprétation little-endian (LSB, MSB)
+ lsb, msb = data[0], data[1]
+ distance = msb << 8 | lsb
+ return distance
+
+def main():
+ with serial.Serial(SERIAL_PORT, BAUDRATE, timeout=TIMEOUT) as ser:
+ print("Connexion ouverte sur", SERIAL_PORT)
+
+ mode = input("Mode (one / continuous / stop) ? ").strip().lower()
+
+ if mode == "one":
+ send_command(ser, CMD_ONE)
+ print("Mesure unique demandée. Attente résultat...")
+ time.sleep(0.05)
+ distance = read_distance(ser)
+ if distance is not None:
+ print(f"Distance mesurée : {distance} cm")
+ else:
+ print("Erreur : distance non reçue.")
+
+ elif mode == "continuous":
+ send_command(ser, CMD_CONTINUOUS)
+ print("Mesures continues (CTRL+C pour stopper) :")
+ try:
+ while True:
+ distance = read_distance(ser)
+ if distance is not None:
+ print(f"Distance : {distance} cm")
+ else:
+ print("... (aucune donnée reçue)")
+ time.sleep(0.1)
+ except KeyboardInterrupt:
+ send_command(ser, CMD_STOP)
+ print("\nMesure continue arrêtée.")
+
+ elif mode == "stop":
+ send_command(ser, CMD_STOP)
+ print("Commande STOP envoyée.")
+
+ else:
+ print("Commande invalide.")
+
+if __name__ == "__main__":
+ main()
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
index 0788abc..b4c2f4e 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
@@ -1,6 +1,6 @@
`timescale 1ns/1ps
-module tb_uart;
+module tb_ultrason_commands;
reg clk = 0;
reg tx_enable = 0;
@@ -11,19 +11,32 @@ module tb_uart;
reg rx_received;
wire rx_enable = 1'b1;
- wire pin;
+ wire rx,tx;
always #18.5 clk = ~clk;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
+ ultrasonic_sensor ultrasonic_sensor_instance (
+ .clk(clk),
+ .signal(ultrason_sig)
+ );
+
+ top_uart_ultrason_command top_uart_ultrason_command_instance (
+ .clk(clk),
+ .rx(rx),
+ .tx(tx),
+ .ultrason_sig(ultrason_sig),
+ .leds()
+ );
+
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
- .rx_pin(pin),
+ .rx_pin(tx),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
@@ -37,7 +50,7 @@ module tb_uart;
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
- .tx(pin),
+ .tx(rx),
.rst_p(1'b0)
);
@@ -45,37 +58,11 @@ module tb_uart;
$dumpfile("runs/uart.vcd");
$dumpvars(0, tb_uart);
- $display("======== Start UART LOOPBACK test =========");
+ $display("======== Start UART ULTRASONIC COMMANDS =========");
- #100;
+
- data_in <= 8'd234; // 234
- tx_enable <= 1;
- wait(tx_ready == 1'b0);
- tx_enable <= 0;
-
- // Attendre
- wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
-
- $display("Data received: %d", data_out); // Afficher la valeur recu
- $display("Data expected: %d", data_in); // Afficher la valeur envoyee
-
- #1000;
-
- wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
-
- data_in <= 8'd202; // 202
- tx_enable <= 1;
- wait(tx_ready == 1'b0);
- tx_enable <= 0;
-
- // Attendre
- wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
-
- $display("Data received: %d", data_out); // Afficher la valeur recu
- $display("Data expected: %d", data_in); // Afficher la valeur envoyee
-
- $display("======== END UART TX test =========");
+ $display("======== END UART ULTRASONIC COMMANDS =========");
#1000;
$stop;