diff --git a/Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst b/Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst
index 8bdd959..5aa9a2b 100644
--- a/Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst
+++ b/Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst
@@ -1,7 +1,9 @@
-IO_LOC "o_tx" 73;
+#IO_LOC "o_tx" 73;
+IO_LOC "o_tx" 69;
 IO_PORT "o_tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 
-IO_LOC "i_rx" 74;
+IO_LOC "i_rx" 70;
+#IO_LOC "i_rx" 74;
 IO_PORT "i_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 
 IO_LOC "i_clk" 4;
diff --git a/Semaine_7/ESP32/leds_commands/project.sh b/Semaine_7/ESP32/leds_commands/project.sh
old mode 100644
new mode 100755
diff --git a/Semaine_7/ESP32/leds_commands/scripts/linux/build.sh b/Semaine_7/ESP32/leds_commands/scripts/linux/build.sh
index dd0e9c7..86c16ab 100644
--- a/Semaine_7/ESP32/leds_commands/scripts/linux/build.sh
+++ b/Semaine_7/ESP32/leds_commands/scripts/linux/build.sh
@@ -6,7 +6,7 @@ cd "$(dirname "$0")/../.." || exit 1
 # Config de base
 DEVICE="GW2AR-LV18QN88C8/I7"
 BOARD="tangnano20k"
-TOP="dht11_uart_top"
+TOP="fpga_wifi_led"
 CST_FILE="$TOP.cst"
 JSON_FILE="runs/$TOP.json"
 PNR_JSON="runs/pnr_$TOP.json"
@@ -16,7 +16,7 @@ BITSTREAM="runs/$TOP.fs"
 mkdir -p runs
 
 echo "=== Étape 1 : Synthèse avec Yosys ==="
-yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v  IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top $TOP -json $JSON_FILE"
+yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v IP/verilog/rxuartlite.v; synth_gowin -top $TOP -json $JSON_FILE"
 if [ $? -ne 0 ]; then
   echo "=== Erreur lors de la synthèse ==="
   exit 1
@@ -37,7 +37,7 @@ if [ $? -ne 0 ]; then
 fi
 
 echo "=== Étape 4 : Flash avec openFPGALoader ==="
-sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
+sudo /home/louis/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
 if [ $? -ne 0 ]; then
   echo "=== Erreur lors du flash ==="
   exit 1
diff --git a/Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino b/Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino
index a3d1dce..ea6813a 100644
--- a/Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino
+++ b/Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino
@@ -20,11 +20,11 @@ bool touchDetected = false;
 // UART pins for FPGA communication
 const int UART_RX_PIN = 16; // GPIO16 - RX from FPGA
 const int UART_TX_PIN = 17; // GPIO17 - TX to FPGA
-const int UART_BAUD = 500000;
+const int UART_BAUD = 115200;
  
 void setup() {
   // Initialize Serial for USB debugging (115200 baud)
-  Serial.begin(115200);
+  Serial.begin(115200); 
   
   // Initialize Serial2 for FPGA communication
   Serial2.begin(UART_BAUD, SERIAL_8N1, UART_RX_PIN, UART_TX_PIN);
diff --git a/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v b/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
index 080d31a..2ef940a 100644
--- a/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
+++ b/Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
@@ -8,8 +8,8 @@ module fpga_wifi_led (
     
 
     // === PARAMÈTRES ===
-    localparam CLK_FREQ = 57_857_142;
-    localparam BAUD_RATE = 500000;
+    localparam CLK_FREQ = 27_000_000; //57_857_142;
+    localparam BAUD_RATE = 115200;
     localparam FIFO_SIZE = 8;
 
     // === SIGNAUX UART RX ===
@@ -30,7 +30,7 @@ module fpga_wifi_led (
 
     wire out_clk;
     wire clk_lock;
-
+/*
     rPLL #( // For GW1NR-9C C6/I5 (Tang Nano 9K proto dev board)
     .FCLKIN("27"),
     .IDIV_SEL(6), // -> PFD = 3.857142857142857 MHz (range: 3-400 MHz)
@@ -41,6 +41,9 @@ module fpga_wifi_led (
     .CLKOUT(out_clk), // 50.142857142857146 MHz
     .LOCK(clk_lock)
     );
+    */
+
+    assign out_clk = i_clk;
 
     // === ÉTATS DE LA FSM ===
     localparam  IDLE = 2'd0,
diff --git a/Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py b/Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py
index b032162..5b0fa13 100644
--- a/Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py
+++ b/Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py
@@ -2,7 +2,7 @@ import socket
 import time
 
 # Remplace cette IP par celle affichée par l'ESP32 dans le terminal série
-ESP32_IP = "192.168.1.105"
+ESP32_IP = "172.20.10.13"
 ESP32_PORT = 1234
 
 def send_bytes(commands):