From 35f84d9d16dc042190066a163edfc5517929d773 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Tue, 27 May 2025 10:12:31 +0200 Subject: [PATCH] recodage de lundi --- .../DHT11_UART/IP/verilog/dht11_interface.v | 103 +++++++----------- .../DHT11_UART/scripts/windows/build.bat | 12 +- .../DHT11_UART/src/verilog/dht11_uart_top.v | 49 ++++++--- 3 files changed, 81 insertions(+), 83 deletions(-) diff --git a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v index a395468..7c58677 100644 --- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v +++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v @@ -6,41 +6,40 @@ module dht11_interface #( input wire i_start, output reg o_dht11_data_ready, output reg o_busy, - output reg [7:0] o_temp_data, - output reg [7:0] o_hum_data, - output reg o_dht11_error + output reg [15:0] o_temp_data, + output reg [15:0] o_hum_data, + output reg [7:0] o_checksum, + output reg [3:0] o_state ); // === DHT11 INTERFACE === // === PARAMÈTRES === localparam T_18MS = CLK_FREQ * 18 / 1_000; // cycles pour 18ms a partir - localparam T_80US = CLK_FREQ * 81 / 1_000_000; - localparam T_79US = CLK_FREQ * 79 / 1_000_000; - localparam T_71US = CLK_FREQ * 71 / 1_000_000; - localparam T_51US = CLK_FREQ * 51 / 1_000_000; + localparam T_80US = CLK_FREQ * 90 / 1_000_000; + localparam T_79US = CLK_FREQ * 70 / 1_000_000; + localparam T_71US = CLK_FREQ * 81 / 1_000_000; + localparam T_51US = CLK_FREQ * 58 / 1_000_000; localparam T_50US = CLK_FREQ * 50 / 1_000_000; localparam T_49US = CLK_FREQ * 49 / 1_000_000; - localparam T_41US = CLK_FREQ * 41 / 1_000_000; - localparam T_28US = CLK_FREQ * 28 / 1_000_000; - localparam T_26US = CLK_FREQ * 26 / 1_000_000; - localparam T_20US = CLK_FREQ * 20 / 1_000_000; + localparam T_41US = CLK_FREQ * 50 / 1_000_000; + localparam T_28US = CLK_FREQ * 32 / 1_000_000; + localparam T_26US = CLK_FREQ * 25 / 1_000_000; + localparam T_20US = CLK_FREQ * 18 / 1_000_000; // === Signal bidirectionnel === reg sig_dir; reg sig_out; - wire sig_in; + reg sig_in; assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz) - assign sig_in = io_dht11_sig; + // === REGISTRES === reg [3:0] state; reg [31:0] timer; - reg [7:0] temp_data, hum_data; - reg [7:0] temp_dec, hum_dec, checksum; reg [2:0] bit_count; reg [5:0] bit_index; reg [39:0] raw_data; @@ -70,6 +69,7 @@ module dht11_interface #( // === FSM principale === always @(posedge i_clk) begin + sig_in <= io_dht11_sig; case (state) IDLE: begin @@ -102,111 +102,88 @@ module dht11_interface #( end WAIT_RESPONSE: begin + o_state <= state; + timer <= timer + 1; if (sig_in == 0) begin - if (timer > T_20US && timer < T_41US) begin - + state <= RESPONSE_LOW; timer <= 0; - end else begin - state <= ERROR; - end - end else if (timer > T_41US) begin - state <= ERROR; + end end RESPONSE_LOW: begin + o_state <= state; timer <= timer + 1; if (sig_in == 1) begin - if (timer > T_79US && timer < T_80US) begin + timer <= 0; state <= RESPONSE_HIGH; - end else begin - state <= ERROR; - end - end else if (timer > T_80US) begin - state <= ERROR; + end end RESPONSE_HIGH: begin timer <= timer + 1; - + o_state <= state; if (sig_in == 0) begin - if (timer > T_79US && timer < T_80US) begin + timer <= 0; state <= READ_BITS_LOW; - end else begin - state <= ERROR; - end - end else if (timer > T_80US) begin - state <= ERROR; + end end READ_BITS_LOW: begin + o_state <= state; timer <= timer + 1; if (sig_in == 1) begin - if (timer > T_49US && timer < T_51US) begin + timer <= 0; state <= READ_BITS_HIGH; - end else begin - state <= ERROR; - end - end else if (timer > T_51US) begin - state <= ERROR; + end end READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1 + o_state <= state; timer <= timer + 1; if (sig_in == 0) begin - if (timer <= T_26US) begin - state <= ERROR; - end + raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us timer <= 0; bit_index <= bit_index + 1; - if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit + if (bit_index == 39) begin state <= DONE; end else begin state <= READ_BITS_LOW; end - end else if (timer > T_71US) begin - state <= ERROR; end end DONE: begin - hum_data <= raw_data[39:32]; - hum_dec <= raw_data[31:24]; - temp_data <= raw_data[23:16]; - temp_dec <= raw_data[15:8]; - checksum <= raw_data[7:0]; - + o_state <= state; if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin - o_hum_data <= raw_data[39:32]; - o_temp_data <= raw_data[23:16]; + o_hum_data <= raw_data[39:24]; + o_temp_data <= raw_data[23:8]; o_dht11_data_ready <= 1; - end else begin - o_dht11_error <= 1; - end + end + + o_hum_data <= raw_data[39:24]; + o_temp_data <= raw_data[23:8]; + o_checksum <= raw_data[7:0]; + o_dht11_data_ready <= 1; o_busy <= 0; state <= IDLE; end - ERROR: begin - o_dht11_error <= 1; - state <= IDLE; - end - endcase end diff --git a/Semaine_7/DHT11_UART/scripts/windows/build.bat b/Semaine_7/DHT11_UART/scripts/windows/build.bat index 89520d5..39a6de9 100644 --- a/Semaine_7/DHT11_UART/scripts/windows/build.bat +++ b/Semaine_7/DHT11_UART/scripts/windows/build.bat @@ -2,24 +2,26 @@ setlocal rem === Aller à la racine du projet === -cd /d %~dp0\.. +cd /d %~dp0\..\.. +echo Script lancé depuis : %cd% + rem === Config de base === set DEVICE=GW2AR-LV18QN88C8/I7 set BOARD=tangnano20k -set TOP=top_uart_ultrason_command +set TOP=dht11_uart_top set CST_FILE=%TOP%.cst set JSON_FILE=runs/%TOP%.json set PNR_JSON=runs/pnr_%TOP%.json set BITSTREAM=runs/%TOP%.fs rem === Créer le dossier runs si nécessaire === -if not exist runs ( - mkdir runs +if not exist ../runs ( + mkdir ../runs ) echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === diff --git a/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v b/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v index 346a78f..ec29ae2 100644 --- a/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v +++ b/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v @@ -16,9 +16,10 @@ wire tx_fifo_full; reg i_start; wire o_dht11_data_ready; wire o_busy; -wire [7:0] o_temp_data; -wire [7:0] o_hum_data; -wire o_dht11_error; +wire [15:0] o_temp_data; +wire [15:0] o_hum_data; +wire [7:0] o_checksum; +wire [3:0] dht11_state; uart_tx_fifo #( .CLK_FREQ(CLK_FREQ), @@ -40,16 +41,25 @@ dht11_interface dht11_inst ( .o_busy(o_busy), .o_temp_data(o_temp_data), .o_hum_data(o_hum_data), - .o_dht11_error(o_dht11_error) + .o_checksum(o_checksum), + .o_state(dht11_state), ); // === FSM === -localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3; -reg [2:0] state = X; +localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3, SEND_FIFO3 = 5, SEND_FIFO4 = 6; +reg [3:0] state = X; reg [31:0] delay_counter = 0; reg strobe2s = 0; reg [7:0] data_fifo = 30; +initial begin + state = X; + i_start = 0; + wr_en = 0; + wr_data = 0; + leds = 6'b000000; +end + // 2s counter always_ff @(posedge clk) begin if (delay_counter == CLK_FREQ * 2 - 1) begin @@ -60,17 +70,17 @@ always_ff @(posedge clk) begin strobe2s <= 0; end - leds[5] <= !o_dht11_error; + end always_ff @(posedge clk) begin + leds <= {dht11_state, 1'b1}; case (state) X: begin i_start <= 0; wr_en <= 1; wr_data <= data_fifo; state <= WAIT; - leds [4:0] = 5'b11110; end WAIT: begin i_start <= 0; @@ -79,30 +89,39 @@ always_ff @(posedge clk) begin state <= MESURE; i_start <= 1; end - leds [4:0] = 5'b11100; end MESURE: begin i_start <= 0; if (o_dht11_data_ready) begin state <= SEND_FIFO1; - wr_data <= o_temp_data; + wr_data <= o_hum_data[15:8]; // Send temperature MSB wr_en <= 1; end - leds [4:0] = 5'b11000; end SEND_FIFO1: begin - wr_data <= o_hum_data; + wr_data <= o_hum_data[7:0]; // Send temperature LSB wr_en <= 1; state <= SEND_FIFO2; - leds [4:0] = 5'b10000; end SEND_FIFO2: begin - wr_en <= 0; + wr_data <= o_temp_data[15:8]; // Send hum MSB + wr_en <= 1; + state <= SEND_FIFO3; + end + + SEND_FIFO3: begin + wr_data <= o_temp_data[7:0]; // Send hum LSB + wr_en <= 1; + state <= SEND_FIFO4; + end + + SEND_FIFO4: begin + wr_data <= o_checksum; // Send checksum + wr_en <= 1; state <= WAIT; - leds [4:0] = 5'b00000; end default: state <= WAIT;