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Init et début de réflexion sur le projet

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Gamenight77
2025-04-22 09:56:06 +02:00
parent 39acfbe25b
commit 3bb56e2f57
48 changed files with 21 additions and 0 deletions
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29
Semaine_1/Capteur_recule_avec_deux_broche/Distance_display_led/distance_display_led.v Normal file
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module distance_display_led (
input wire [8:0] distance,
output reg [5:0] leds
);
// Constante
parameter MIN_DIST = 2;
parameter MAX_DIST = 349;
parameter LEVELS = 5;
parameter PART_SIZE = (MAX_DIST - MIN_DIST + 1) / LEVELS;
always @(*) begin
if (distance <= MIN_DIST + PART_SIZE*0)
leds = 6'b111111;
else if (distance <= MIN_DIST + PART_SIZE*1)
leds = 6'b111110;
else if (distance <= MIN_DIST + PART_SIZE*2)
leds = 6'b111100;
else if (distance <= MIN_DIST + PART_SIZE*3)
leds = 6'b111000;
else if (distance <= MIN_DIST + PART_SIZE*4)
leds = 6'b110000;
else if (distance <= MIN_DIST + PART_SIZE*5)
leds = 6'b100000;
else
leds = 6'b000000;
end
endmodule

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Semaine_1/Capteur_recule_avec_deux_broche/Distance_display_led/distance_display_led.vcd Normal file
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$date
Wed Apr 16 14:03:22 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb_distance_display_led $end
$var wire 6 ! leds [5:0] $end
$var reg 9 " distance [8:0] $end
$var integer 32 # i [31:0] $end
$scope module uut $end
$var wire 9 $ distance [8:0] $end
$var parameter 32 % LEVELS $end
$var parameter 32 & MAX_DIST $end
$var parameter 32 ' MIN_DIST $end
$var parameter 34 ( PART_SIZE $end
$var reg 6 ) leds [5:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1000101 (
b10 '
b101011101 &
b101 %
$end
#0
$dumpvars
b111111 )
b0 $
b0 #
b0 "
b111111 !
$end
#10
b111110 !
b111110 )
b1010 "
b1010 $
b1010 #
#20
b10100 "
b10100 $
b10100 #
#30
b11110 "
b11110 $
b11110 #
#40
b101000 "
b101000 $
b101000 #
#50
b110010 "
b110010 $
b110010 #
#60
b111100 "
b111100 $
b111100 #
#70
b1000110 "
b1000110 $
b1000110 #
#80
b111100 !
b111100 )
b1010000 "
b1010000 $
b1010000 #
#90
b1011010 "
b1011010 $
b1011010 #
#100
b1100100 "
b1100100 $
b1100100 #
#110
b1101110 "
b1101110 $
b1101110 #
#120
b1111000 "
b1111000 $
b1111000 #
#130
b10000010 "
b10000010 $
b10000010 #
#140
b10001100 "
b10001100 $
b10001100 #
#150
b111000 !
b111000 )
b10010110 "
b10010110 $
b10010110 #
#160
b10100000 "
b10100000 $
b10100000 #
#170
b10101010 "
b10101010 $
b10101010 #
#180
b10110100 "
b10110100 $
b10110100 #
#190
b10111110 "
b10111110 $
b10111110 #
#200
b11001000 "
b11001000 $
b11001000 #
#210
b110000 !
b110000 )
b11010010 "
b11010010 $
b11010010 #
#220
b11011100 "
b11011100 $
b11011100 #
#230
b11100110 "
b11100110 $
b11100110 #
#240
b11110000 "
b11110000 $
b11110000 #
#250
b11111010 "
b11111010 $
b11111010 #
#260
b100000100 "
b100000100 $
b100000100 #
#270
b100001110 "
b100001110 $
b100001110 #
#280
b100000 !
b100000 )
b100011000 "
b100011000 $
b100011000 #
#290
b100100010 "
b100100010 $
b100100010 #
#300
b100101100 "
b100101100 $
b100101100 #
#310
b100110110 "
b100110110 $
b100110110 #
#320
b101000000 "
b101000000 $
b101000000 #
#330
b101001010 "
b101001010 $
b101001010 #
#340
b101010100 "
b101010100 $
b101010100 #
#350
b0 !
b0 )
b101011110 "
b101011110 $
b101011110 #
#360
b101101000 "
b101101000 $
b101101000 #
#370
b101110010 "
b101110010 $
b101110010 #
#380
b101111100 "
b101111100 $
b101111100 #
#390
b110000110 "
b110000110 $
b110000110 #
#400
b110010000 "
b110010000 $
b110010000 #
#410
b110011010 #

123
Semaine_1/Capteur_recule_avec_deux_broche/Distance_display_led/distance_display_led_sim Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_000001b2514bb620 .scope module, "tb_distance_display_led" "tb_distance_display_led" 2 1;
.timescale 0 0;
v000001b2514bbe50_0 .var "distance", 8 0;
v000001b2514bbef0_0 .var/i "i", 31 0;
v000001b2515d8150_0 .net "leds", 5 0, v000001b2514be0e0_0; 1 drivers
S_000001b2514bbb30 .scope module, "uut" "distance_display_led" 2 5, 3 1 0, S_000001b2514bb620;
.timescale 0 0;
.port_info 0 /INPUT 9 "distance";
.port_info 1 /OUTPUT 6 "leds";
P_000001b2514bbcc0 .param/l "LEVELS" 0 3 9, +C4<00000000000000000000000000000101>;
P_000001b2514bbcf8 .param/l "MAX_DIST" 0 3 8, +C4<00000000000000000000000101011101>;
P_000001b2514bbd30 .param/l "MIN_DIST" 0 3 7, +C4<00000000000000000000000000000010>;
P_000001b2514bbd68 .param/l "PART_SIZE" 0 3 10, +C4<0000000000000000000000000001000101>;
v000001b2514bbdb0_0 .net "distance", 8 0, v000001b2514bbe50_0; 1 drivers
v000001b2514be0e0_0 .var "leds", 5 0;
E_000001b2515c8c00 .event anyedge, v000001b2514bbdb0_0;
.scope S_000001b2514bbb30;
T_0 ;
%wait E_000001b2515c8c00;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 2, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.0, 5;
%pushi/vec4 63, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 71, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.2, 5;
%pushi/vec4 62, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.3;
T_0.2 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 140, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.4, 5;
%pushi/vec4 60, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.5;
T_0.4 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 209, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.6, 5;
%pushi/vec4 56, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.7;
T_0.6 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 278, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.8, 5;
%pushi/vec4 48, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.9;
T_0.8 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 347, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.10, 5;
%pushi/vec4 32, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
T_0.11 ;
T_0.9 ;
T_0.7 ;
T_0.5 ;
T_0.3 ;
T_0.1 ;
%jmp T_0;
.thread T_0, $push;
.scope S_000001b2514bb620;
T_1 ;
%vpi_call 2 13 "$dumpfile", "distance_display_led.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001b2514bb620 {0 0 0};
%pushi/vec4 0, 0, 32;
%store/vec4 v000001b2514bbef0_0, 0, 32;
T_1.0 ; Top of for-loop
%load/vec4 v000001b2514bbef0_0;
%cmpi/s 400, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_1.1, 5;
%load/vec4 v000001b2514bbef0_0;
%pad/s 9;
%store/vec4 v000001b2514bbe50_0, 0, 9;
%delay 10, 0;
%vpi_call 2 20 "$display", "Distance: %3d cm => LEDs: %b", v000001b2514bbe50_0, v000001b2515d8150_0 {0 0 0};
T_1.2 ; for-loop step statement
%load/vec4 v000001b2514bbef0_0;
%addi 10, 0, 32;
%store/vec4 v000001b2514bbef0_0, 0, 32;
%jmp T_1.0;
T_1.1 ; for-loop exit label
%vpi_call 2 23 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb_distance_display_led.v";
"distance_display_led.v";

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Semaine_1/Capteur_recule_avec_deux_broche/Distance_display_led/tb_distance_display_led.v Normal file
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module tb_distance_display_led;
reg [8:0] distance;
wire [5:0] leds;
distance_display_led uut (
.distance(distance),
.leds(leds)
);
integer i;
initial begin
$dumpfile("distance_display_led.vcd");
$dumpvars(0, tb_distance_display_led);
// Test de la conversion de distance en LED
for (i = 0; i <= 380; i = i + 10) begin
distance = i;
#10;
$display("Distance: %3d cm => LEDs: %b", distance, leds);
end
$finish;
end
endmodule

73
Semaine_1/Capteur_recule_avec_deux_broche/Ultrasonic/tb_ultrasonic_fpga.v Normal file
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`timescale 1ns/1ps
module tb_ultrasonic_fpga;
reg clk = 0;
reg rst = 1;
reg start = 0;
reg echo = 0;
wire trig_out;
wire [8:0] distance;
time t_start, t_end;
// Clock 27MHz => periode = 37ns
always #18 clk = ~clk;
ultrasonic_fpga uut (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig_out(trig_out),
.distance(distance)
);
initial begin
$dumpfile("ultrasonic.vcd");
$dumpvars(0, tb_ultrasonic_fpga);
// Reset
#100;
rst = 0;
// Start
#100;
start = 1;
#40;
start = 0;
wait (trig_out == 1);
t_start = $time;
// Attendre qu'il redescende
wait (trig_out == 0);
t_end = $time;
$display("Trig HIGH duration: %0dns", t_end - t_start);
if ((t_end - t_start) >= 9500 && (t_end - t_start) <= 10500) begin
$display("Trigger signal is high for 10us.");
#10;
echo = 1;
#5800;// Echo dure 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
echo = 0;
end else begin
$display("Trigger signal is NOT high for 10us.");
end
#500;
// Affiche la distance
if (distance > 0) begin
$display("Distance measured: %d cm", distance);
end else begin
$display("No distance measured.");
end
$finish;
end
endmodule

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Semaine_1/Capteur_recule_avec_deux_broche/Ultrasonic/ultrasonic.vcd Normal file
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71
Semaine_1/Capteur_recule_avec_deux_broche/Ultrasonic/ultrasonic_fpga.v Normal file
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module ultrasonic_fpga #(
parameter integer CLK_FREQ = 27_000_000 // frequence de clk en Hz
)(
input wire clk,
input wire rst,
input wire start, // signal de declenchement
input wire echo, // retour du capteur
output reg trig_out, // signal envoye au capteur
output reg [8:0] distance // distance mesuree
);
reg [2:0] state;
reg [8:0] trig_counter;
reg [15:0] echo_counter;
localparam IDLE = 0, TRIG = 1, WAIT_ECHO = 2, MEASURE_ECHO = 3, DONE = 4;
// Constantes dépendantes de CLK_FREQ
localparam integer TRIG_DURATION_CYCLES = CLK_FREQ / 100_000; // 10us
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion µs -> cm
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= IDLE;
trig_out <= 0;
trig_counter <= 0;
echo_counter <= 0;
distance <= 0;
end else begin
case (state)
IDLE: begin
if (start) begin
state <= TRIG;
end
end
TRIG: begin
if (trig_counter < TRIG_DURATION_CYCLES) begin
trig_out <= 1;
trig_counter <= trig_counter + 1;
end else begin
trig_out <= 0;
trig_counter <= 0;
state <= WAIT_ECHO;
end
end
WAIT_ECHO: begin
if (echo) begin
echo_counter <= 0;
state <= MEASURE_ECHO;
end
end
MEASURE_ECHO: begin
if (echo) begin
echo_counter <= echo_counter + 1;
end else begin
distance <= (echo_counter*1000) / DIST_DIVISOR;
state <= DONE;
end
end
DONE: begin
state <= IDLE;
end
endcase
end
end
endmodule

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Semaine_1/Capteur_recule_avec_deux_broche/Ultrasonic/ultrasonic_sim Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_000002569854ec30 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
.timescale -9 -12;
v00000256985b7a50_0 .var "clk", 0 0;
v00000256985b72d0_0 .net "distance", 15 0, v000002569854e7f0_0; 1 drivers
v00000256985b7870_0 .var "echo", 0 0;
v00000256985b7cd0_0 .var "rst", 0 0;
v00000256985b7f50_0 .var "start", 0 0;
v00000256985b7910_0 .var "t_end", 63 0;
v00000256985b7af0_0 .var "t_start", 63 0;
v00000256985b7d70_0 .net "trig_out", 0 0, v00000256985b7370_0; 1 drivers
E_000002569854ae50 .event anyedge, v00000256985b7370_0;
S_000002569854edc0 .scope module, "uut" "ultrasonic_fpga" 2 17, 3 1 0, S_000002569854ec30;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "start";
.port_info 3 /INPUT 1 "echo";
.port_info 4 /OUTPUT 1 "trig_out";
.port_info 5 /OUTPUT 16 "distance";
P_0000025698560660 .param/l "CLK_FREQ" 0 3 2, +C4<00000001100110111111110011000000>;
P_0000025698560698 .param/l "DIST_DIVISOR" 1 3 20, +C4<00000000000000000000000000000001>;
P_00000256985606d0 .param/l "DONE" 1 3 16, +C4<00000000000000000000000000000100>;
P_0000025698560708 .param/l "IDLE" 1 3 16, +C4<00000000000000000000000000000000>;
P_0000025698560740 .param/l "MEASURE_ECHO" 1 3 16, +C4<00000000000000000000000000000011>;
P_0000025698560778 .param/l "TRIG" 1 3 16, +C4<00000000000000000000000000000001>;
P_00000256985607b0 .param/l "TRIG_DURATION_CYCLES" 1 3 19, +C4<00000000000000000000000100001110>;
P_00000256985607e8 .param/l "WAIT_ECHO" 1 3 16, +C4<00000000000000000000000000000010>;
v000002569854ef50_0 .net "clk", 0 0, v00000256985b7a50_0; 1 drivers
v000002569854e7f0_0 .var "distance", 15 0;
v000002569854c1a0_0 .net "echo", 0 0, v00000256985b7870_0; 1 drivers
v00000256985b74b0_0 .var "echo_counter", 15 0;
v00000256985b7b90_0 .net "rst", 0 0, v00000256985b7cd0_0; 1 drivers
v00000256985b7c30_0 .net "start", 0 0, v00000256985b7f50_0; 1 drivers
v00000256985b7050_0 .var "state", 2 0;
v00000256985b77d0_0 .var "trig_counter", 8 0;
v00000256985b7370_0 .var "trig_out", 0 0;
E_000002569854af10 .event posedge, v00000256985b7b90_0, v000002569854ef50_0;
.scope S_000002569854edc0;
T_0 ;
%wait E_000002569854af10;
%load/vec4 v00000256985b7b90_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000256985b7370_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v00000256985b77d0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000256985b74b0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000002569854e7f0_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v00000256985b7050_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%jmp T_0.7;
T_0.2 ;
%load/vec4 v00000256985b7c30_0;
%flag_set/vec4 8;
%jmp/0xz T_0.8, 8;
%pushi/vec4 1, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
T_0.8 ;
%jmp T_0.7;
T_0.3 ;
%load/vec4 v00000256985b77d0_0;
%pad/u 32;
%cmpi/u 270, 0, 32;
%jmp/0xz T_0.10, 5;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000256985b7370_0, 0;
%load/vec4 v00000256985b77d0_0;
%addi 1, 0, 9;
%assign/vec4 v00000256985b77d0_0, 0;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000256985b7370_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v00000256985b77d0_0, 0;
%pushi/vec4 2, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
T_0.11 ;
%jmp T_0.7;
T_0.4 ;
%load/vec4 v000002569854c1a0_0;
%flag_set/vec4 8;
%jmp/0xz T_0.12, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000256985b74b0_0, 0;
%pushi/vec4 3, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
T_0.12 ;
%jmp T_0.7;
T_0.5 ;
%load/vec4 v000002569854c1a0_0;
%flag_set/vec4 8;
%jmp/0xz T_0.14, 8;
%load/vec4 v00000256985b74b0_0;
%addi 1, 0, 16;
%assign/vec4 v00000256985b74b0_0, 0;
%jmp T_0.15;
T_0.14 ;
%load/vec4 v00000256985b74b0_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%div;
%pad/u 16;
%assign/vec4 v000002569854e7f0_0, 0;
%pushi/vec4 4, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
T_0.15 ;
%jmp T_0.7;
T_0.6 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000256985b7050_0, 0;
%jmp T_0.7;
T_0.7 ;
%pop/vec4 1;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_000002569854ec30;
T_1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7a50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000256985b7cd0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7f50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7870_0, 0, 1;
%end;
.thread T_1;
.scope S_000002569854ec30;
T_2 ;
%delay 18000, 0;
%load/vec4 v00000256985b7a50_0;
%inv;
%store/vec4 v00000256985b7a50_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_000002569854ec30;
T_3 ;
%vpi_call 2 27 "$dumpfile", "ultrasonic.vcd" {0 0 0};
%vpi_call 2 28 "$dumpvars", 32'sb00000000000000000000000000000000, S_000002569854ec30 {0 0 0};
%delay 100000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7cd0_0, 0, 1;
%delay 100000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000256985b7f50_0, 0, 1;
%delay 40000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7f50_0, 0, 1;
T_3.0 ;
%load/vec4 v00000256985b7d70_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.1, 6;
%wait E_000002569854ae50;
%jmp T_3.0;
T_3.1 ;
%vpi_func 2 41 "$time" 64 {0 0 0};
%store/vec4 v00000256985b7af0_0, 0, 64;
T_3.2 ;
%load/vec4 v00000256985b7d70_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.3, 6;
%wait E_000002569854ae50;
%jmp T_3.2;
T_3.3 ;
%vpi_func 2 45 "$time" 64 {0 0 0};
%store/vec4 v00000256985b7910_0, 0, 64;
%load/vec4 v00000256985b7910_0;
%load/vec4 v00000256985b7af0_0;
%sub;
%vpi_call 2 47 "$display", "Trig HIGH duration: %0dns", S<0,vec4,u64> {1 0 0};
%load/vec4 v00000256985b7910_0;
%load/vec4 v00000256985b7af0_0;
%sub;
%cmpi/u 9500, 0, 64;
%flag_inv 5; GE is !LT
%flag_get/vec4 5;
%jmp/0 T_3.6, 5;
%load/vec4 v00000256985b7910_0;
%load/vec4 v00000256985b7af0_0;
%sub;
%cmpi/u 10500, 0, 64;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
T_3.6;
%flag_set/vec4 8;
%jmp/0xz T_3.4, 8;
%vpi_call 2 50 "$display", "Trigger signal is high for 10us." {0 0 0};
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000256985b7870_0, 0, 1;
%delay 5800000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000256985b7870_0, 0, 1;
%jmp T_3.5;
T_3.4 ;
%vpi_call 2 58 "$display", "Trigger signal is NOT high for 10us." {0 0 0};
T_3.5 ;
%delay 500000, 0;
%load/vec4 v00000256985b72d0_0;
%pad/u 32;
%cmpi/u 0, 0, 32;
%flag_or 5, 4; GT is !LE
%flag_inv 5;
%jmp/0xz T_3.7, 5;
%vpi_call 2 65 "$display", "Distance measured: %d cm", v00000256985b72d0_0 {0 0 0};
%jmp T_3.8;
T_3.7 ;
%vpi_call 2 67 "$display", "No distance measured." {0 0 0};
T_3.8 ;
%vpi_call 2 70 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb_ultrasonic_fpga.v";
"ultrasonic_fpga.v";

61
Semaine_1/Capteur_recule_avec_deux_broche/tb_top_ultrasonic_led.v Normal file
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`timescale 1ns/1ps
module tb_top_ultrasonic_led;
reg clk;
reg rst;
reg start;
reg echo;
wire trig;
wire [5:0] leds;
// Instance du module top
top_ultrasonic_led uut (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig(trig),
.leds(leds)
);
always #18.5 clk = ~clk;
initial begin
// Initialisation
$dumpfile("top_ultrasonic_led.vcd");
$dumpvars(0, tb_top_ultrasonic_led);
clk = 0;
rst = 1;
start = 0;
echo = 0;
#100;
rst = 0;
#50;
start = 1;
#20;
start = 0;
// Attente du signal trig
wait (trig == 1);
$display("TRIG HIGH at %t", $time);
wait (trig == 0);
$display("TRIG LOW at %t", $time);
repeat (500) @(posedge clk);
echo = 1;
#12000
echo = 0;
repeat (500) @(posedge clk);
$display("Leds allumer : %b", leds);
$finish;
end
endmodule

28
Semaine_1/Capteur_recule_avec_deux_broche/top_ultrasonic_led.v Normal file
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module top_ultrasonic_led (
input wire clk,
input wire rst,
input wire start, // bouton ou signal de départ
input wire echo, // signal du capteur
output wire trig, // vers le capteur
output wire [5:0] leds // sorties LED
);
wire [8:0] distance;
// Module de mesure de distance
ultrasonic_fpga ultrasonic_inst (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig_out(trig),
.distance(distance)
);
// Module d'affichage leds
distance_display_led led_display_inst (
.distance(distance),
.leds(leds)
);
endmodule

7911
Semaine_1/Capteur_recule_avec_deux_broche/top_ultrasonic_led.vcd Normal file
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File diff suppressed because it is too large Load Diff

335
Semaine_1/Capteur_recule_avec_deux_broche/top_ultrasonic_led_tb.vvp Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_0000016babb102e0 .scope module, "tb_top_ultrasonic_led" "tb_top_ultrasonic_led" 2 3;
.timescale -9 -12;
v0000016babb7abc0_0 .var "clk", 0 0;
v0000016babb7ada0_0 .var "echo", 0 0;
v0000016babb7a580_0 .net "leds", 5 0, v0000016babb0e8e0_0; 1 drivers
v0000016babb7a260_0 .var "rst", 0 0;
v0000016babb7a620_0 .var "start", 0 0;
v0000016babb7a760_0 .net "trig", 0 0, v0000016babb7a120_0; 1 drivers
E_0000016babb0c2a0 .event posedge, v0000016babb7a4e0_0;
E_0000016babb0c320 .event anyedge, v0000016babb7a120_0;
S_0000016babae6610 .scope module, "uut" "top_ultrasonic_led" 2 13, 3 1 0, S_0000016babb102e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "start";
.port_info 3 /INPUT 1 "echo";
.port_info 4 /OUTPUT 1 "trig";
.port_info 5 /OUTPUT 6 "leds";
v0000016babb7ab20_0 .net "clk", 0 0, v0000016babb7abc0_0; 1 drivers
v0000016babb7af80_0 .net "distance", 8 0, v0000016babb7a440_0; 1 drivers
v0000016babb7a6c0_0 .net "echo", 0 0, v0000016babb7ada0_0; 1 drivers
v0000016babb7a800_0 .net "leds", 5 0, v0000016babb0e8e0_0; alias, 1 drivers
v0000016babb7ac60_0 .net "rst", 0 0, v0000016babb7a260_0; 1 drivers
v0000016babb7a9e0_0 .net "start", 0 0, v0000016babb7a620_0; 1 drivers
v0000016babb7aa80_0 .net "trig", 0 0, v0000016babb7a120_0; alias, 1 drivers
S_0000016babae67a0 .scope module, "led_display_inst" "distance_display_led" 3 23, 4 1 0, S_0000016babae6610;
.timescale 0 0;
.port_info 0 /INPUT 9 "distance";
.port_info 1 /OUTPUT 6 "leds";
P_0000016babae6930 .param/l "LEVELS" 0 4 9, +C4<00000000000000000000000000000101>;
P_0000016babae6968 .param/l "MAX_DIST" 0 4 8, +C4<00000000000000000000000101011101>;
P_0000016babae69a0 .param/l "MIN_DIST" 0 4 7, +C4<00000000000000000000000000000010>;
P_0000016babae69d8 .param/l "PART_SIZE" 0 4 10, +C4<0000000000000000000000000001000101>;
v0000016babb0e7a0_0 .net "distance", 8 0, v0000016babb7a440_0; alias, 1 drivers
v0000016babb0e8e0_0 .var "leds", 5 0;
E_0000016babb1a860 .event anyedge, v0000016babb0e7a0_0;
S_0000016babb23200 .scope module, "ultrasonic_inst" "ultrasonic_fpga" 3 13, 5 1 0, S_0000016babae6610;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "start";
.port_info 3 /INPUT 1 "echo";
.port_info 4 /OUTPUT 1 "trig_out";
.port_info 5 /OUTPUT 9 "distance";
P_0000016babb23390 .param/l "CLK_FREQ" 0 5 2, +C4<00000001100110111111110011000000>;
P_0000016babb233c8 .param/l "DIST_DIVISOR" 1 5 20, +C4<00000000000000000000011000011110>;
P_0000016babb23400 .param/l "DONE" 1 5 16, +C4<00000000000000000000000000000100>;
P_0000016babb23438 .param/l "IDLE" 1 5 16, +C4<00000000000000000000000000000000>;
P_0000016babb23470 .param/l "MEASURE_ECHO" 1 5 16, +C4<00000000000000000000000000000011>;
P_0000016babb234a8 .param/l "TRIG" 1 5 16, +C4<00000000000000000000000000000001>;
P_0000016babb234e0 .param/l "TRIG_DURATION_CYCLES" 1 5 19, +C4<00000000000000000000000100001110>;
P_0000016babb23518 .param/l "WAIT_ECHO" 1 5 16, +C4<00000000000000000000000000000010>;
v0000016babb7a4e0_0 .net "clk", 0 0, v0000016babb7abc0_0; alias, 1 drivers
v0000016babb7a440_0 .var "distance", 8 0;
v0000016babb7a080_0 .net "echo", 0 0, v0000016babb7ada0_0; alias, 1 drivers
v0000016babb7aee0_0 .var "echo_counter", 15 0;
v0000016babb7a940_0 .net "rst", 0 0, v0000016babb7a260_0; alias, 1 drivers
v0000016babb7a8a0_0 .net "start", 0 0, v0000016babb7a620_0; alias, 1 drivers
v0000016babb7a1c0_0 .var "state", 2 0;
v0000016babb7a3a0_0 .var "trig_counter", 8 0;
v0000016babb7a120_0 .var "trig_out", 0 0;
E_0000016babb1a8e0 .event posedge, v0000016babb7a940_0, v0000016babb7a4e0_0;
.scope S_0000016babb23200;
T_0 ;
%wait E_0000016babb1a8e0;
%load/vec4 v0000016babb7a940_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a440_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0000016babb7a1c0_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%jmp T_0.7;
T_0.2 ;
%load/vec4 v0000016babb7a8a0_0;
%flag_set/vec4 8;
%jmp/0xz T_0.8, 8;
%pushi/vec4 1, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.8 ;
%jmp T_0.7;
T_0.3 ;
%load/vec4 v0000016babb7a3a0_0;
%pad/u 32;
%cmpi/u 270, 0, 32;
%jmp/0xz T_0.10, 5;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%load/vec4 v0000016babb7a3a0_0;
%addi 1, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%pushi/vec4 2, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.11 ;
%jmp T_0.7;
T_0.4 ;
%load/vec4 v0000016babb7a080_0;
%flag_set/vec4 8;
%jmp/0xz T_0.12, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%pushi/vec4 3, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.12 ;
%jmp T_0.7;
T_0.5 ;
%load/vec4 v0000016babb7a080_0;
%flag_set/vec4 8;
%jmp/0xz T_0.14, 8;
%load/vec4 v0000016babb7aee0_0;
%addi 1, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%jmp T_0.15;
T_0.14 ;
%load/vec4 v0000016babb7aee0_0;
%pad/u 32;
%muli 1000, 0, 32;
%pushi/vec4 1566, 0, 32;
%div;
%pad/u 9;
%assign/vec4 v0000016babb7a440_0, 0;
%pushi/vec4 4, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.15 ;
%jmp T_0.7;
T_0.6 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
%jmp T_0.7;
T_0.7 ;
%pop/vec4 1;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0000016babae67a0;
T_1 ;
%wait E_0000016babb1a860;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 2, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.0, 5;
%pushi/vec4 63, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 71, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.2, 5;
%pushi/vec4 62, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.3;
T_1.2 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 140, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.4, 5;
%pushi/vec4 60, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.5;
T_1.4 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 209, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.6, 5;
%pushi/vec4 56, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.7;
T_1.6 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 278, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.8, 5;
%pushi/vec4 48, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.9;
T_1.8 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 347, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.10, 5;
%pushi/vec4 32, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.11;
T_1.10 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
T_1.11 ;
T_1.9 ;
T_1.7 ;
T_1.5 ;
T_1.3 ;
T_1.1 ;
%jmp T_1;
.thread T_1, $push;
.scope S_0000016babb102e0;
T_2 ;
%delay 18500, 0;
%load/vec4 v0000016babb7abc0_0;
%inv;
%store/vec4 v0000016babb7abc0_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_0000016babb102e0;
T_3 ;
%vpi_call 2 26 "$dumpfile", "top_ultrasonic_led.vcd" {0 0 0};
%vpi_call 2 27 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000016babb102e0 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7abc0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7a260_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%delay 100000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a260_0, 0, 1;
%delay 50000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
%delay 20000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
T_3.0 ;
%load/vec4 v0000016babb7a760_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.1, 6;
%wait E_0000016babb0c320;
%jmp T_3.0;
T_3.1 ;
%vpi_call 2 44 "$display", "TRIG HIGH at %t", $time {0 0 0};
T_3.2 ;
%load/vec4 v0000016babb7a760_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.3, 6;
%wait E_0000016babb0c320;
%jmp T_3.2;
T_3.3 ;
%vpi_call 2 46 "$display", "TRIG LOW at %t", $time {0 0 0};
%pushi/vec4 500, 0, 32;
T_3.4 %dup/vec4;
%cmpi/s 0, 0, 32;
%jmp/1xz T_3.5, 5;
%jmp/1 T_3.5, 4;
%subi 1, 0, 32;
%wait E_0000016babb0c2a0;
%jmp T_3.4;
T_3.5 ;
%pop/vec4 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%delay 18000000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%pushi/vec4 500, 0, 32;
T_3.6 %dup/vec4;
%cmpi/s 0, 0, 32;
%jmp/1xz T_3.7, 5;
%jmp/1 T_3.7, 4;
%subi 1, 0, 32;
%wait E_0000016babb0c2a0;
%jmp T_3.6;
T_3.7 ;
%pop/vec4 1;
%vpi_call 2 56 "$display", "LEDs allumer : %b", v0000016babb7a580_0 {0 0 0};
%vpi_call 2 58 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"tb_top_ultrasonic_led.v";
"top_ultrasonic_led.v";
"Distance_display_led/distance_display_led.v";
"Ultrasonic/ultrasonic_fpga.v";

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Semaine_1/Capteur_recule_bidirectionel/Distance_display_led/distance_display_led.v Normal file
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module distance_display_led (
input wire [8:0] distance,
output reg [5:0] leds
);
// Constante
parameter MIN_DIST = 2;
parameter MAX_DIST = 349;
parameter LEVELS = 5;
parameter PART_SIZE = (MAX_DIST - MIN_DIST + 1) / LEVELS;
always @(*) begin
if (distance <= MIN_DIST + PART_SIZE*0)
leds = 6'b111111;
else if (distance <= MIN_DIST + PART_SIZE*1)
leds = 6'b111110;
else if (distance <= MIN_DIST + PART_SIZE*2)
leds = 6'b111100;
else if (distance <= MIN_DIST + PART_SIZE*3)
leds = 6'b111000;
else if (distance <= MIN_DIST + PART_SIZE*4)
leds = 6'b110000;
else if (distance <= MIN_DIST + PART_SIZE*5)
leds = 6'b100000;
else
leds = 6'b000000;
end
endmodule

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Semaine_1/Capteur_recule_bidirectionel/Distance_display_led/distance_display_led.vcd Normal file
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$date
Wed Apr 16 14:03:22 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb_distance_display_led $end
$var wire 6 ! leds [5:0] $end
$var reg 9 " distance [8:0] $end
$var integer 32 # i [31:0] $end
$scope module uut $end
$var wire 9 $ distance [8:0] $end
$var parameter 32 % LEVELS $end
$var parameter 32 & MAX_DIST $end
$var parameter 32 ' MIN_DIST $end
$var parameter 34 ( PART_SIZE $end
$var reg 6 ) leds [5:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1000101 (
b10 '
b101011101 &
b101 %
$end
#0
$dumpvars
b111111 )
b0 $
b0 #
b0 "
b111111 !
$end
#10
b111110 !
b111110 )
b1010 "
b1010 $
b1010 #
#20
b10100 "
b10100 $
b10100 #
#30
b11110 "
b11110 $
b11110 #
#40
b101000 "
b101000 $
b101000 #
#50
b110010 "
b110010 $
b110010 #
#60
b111100 "
b111100 $
b111100 #
#70
b1000110 "
b1000110 $
b1000110 #
#80
b111100 !
b111100 )
b1010000 "
b1010000 $
b1010000 #
#90
b1011010 "
b1011010 $
b1011010 #
#100
b1100100 "
b1100100 $
b1100100 #
#110
b1101110 "
b1101110 $
b1101110 #
#120
b1111000 "
b1111000 $
b1111000 #
#130
b10000010 "
b10000010 $
b10000010 #
#140
b10001100 "
b10001100 $
b10001100 #
#150
b111000 !
b111000 )
b10010110 "
b10010110 $
b10010110 #
#160
b10100000 "
b10100000 $
b10100000 #
#170
b10101010 "
b10101010 $
b10101010 #
#180
b10110100 "
b10110100 $
b10110100 #
#190
b10111110 "
b10111110 $
b10111110 #
#200
b11001000 "
b11001000 $
b11001000 #
#210
b110000 !
b110000 )
b11010010 "
b11010010 $
b11010010 #
#220
b11011100 "
b11011100 $
b11011100 #
#230
b11100110 "
b11100110 $
b11100110 #
#240
b11110000 "
b11110000 $
b11110000 #
#250
b11111010 "
b11111010 $
b11111010 #
#260
b100000100 "
b100000100 $
b100000100 #
#270
b100001110 "
b100001110 $
b100001110 #
#280
b100000 !
b100000 )
b100011000 "
b100011000 $
b100011000 #
#290
b100100010 "
b100100010 $
b100100010 #
#300
b100101100 "
b100101100 $
b100101100 #
#310
b100110110 "
b100110110 $
b100110110 #
#320
b101000000 "
b101000000 $
b101000000 #
#330
b101001010 "
b101001010 $
b101001010 #
#340
b101010100 "
b101010100 $
b101010100 #
#350
b0 !
b0 )
b101011110 "
b101011110 $
b101011110 #
#360
b101101000 "
b101101000 $
b101101000 #
#370
b101110010 "
b101110010 $
b101110010 #
#380
b101111100 "
b101111100 $
b101111100 #
#390
b110000110 "
b110000110 $
b110000110 #
#400
b110010000 "
b110010000 $
b110010000 #
#410
b110011010 #

123
Semaine_1/Capteur_recule_bidirectionel/Distance_display_led/distance_display_led_sim Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_000001b2514bb620 .scope module, "tb_distance_display_led" "tb_distance_display_led" 2 1;
.timescale 0 0;
v000001b2514bbe50_0 .var "distance", 8 0;
v000001b2514bbef0_0 .var/i "i", 31 0;
v000001b2515d8150_0 .net "leds", 5 0, v000001b2514be0e0_0; 1 drivers
S_000001b2514bbb30 .scope module, "uut" "distance_display_led" 2 5, 3 1 0, S_000001b2514bb620;
.timescale 0 0;
.port_info 0 /INPUT 9 "distance";
.port_info 1 /OUTPUT 6 "leds";
P_000001b2514bbcc0 .param/l "LEVELS" 0 3 9, +C4<00000000000000000000000000000101>;
P_000001b2514bbcf8 .param/l "MAX_DIST" 0 3 8, +C4<00000000000000000000000101011101>;
P_000001b2514bbd30 .param/l "MIN_DIST" 0 3 7, +C4<00000000000000000000000000000010>;
P_000001b2514bbd68 .param/l "PART_SIZE" 0 3 10, +C4<0000000000000000000000000001000101>;
v000001b2514bbdb0_0 .net "distance", 8 0, v000001b2514bbe50_0; 1 drivers
v000001b2514be0e0_0 .var "leds", 5 0;
E_000001b2515c8c00 .event anyedge, v000001b2514bbdb0_0;
.scope S_000001b2514bbb30;
T_0 ;
%wait E_000001b2515c8c00;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 2, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.0, 5;
%pushi/vec4 63, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 71, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.2, 5;
%pushi/vec4 62, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.3;
T_0.2 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 140, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.4, 5;
%pushi/vec4 60, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.5;
T_0.4 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 209, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.6, 5;
%pushi/vec4 56, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.7;
T_0.6 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 278, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.8, 5;
%pushi/vec4 48, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.9;
T_0.8 ;
%load/vec4 v000001b2514bbdb0_0;
%pad/u 34;
%cmpi/u 347, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_0.10, 5;
%pushi/vec4 32, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v000001b2514be0e0_0, 0, 6;
T_0.11 ;
T_0.9 ;
T_0.7 ;
T_0.5 ;
T_0.3 ;
T_0.1 ;
%jmp T_0;
.thread T_0, $push;
.scope S_000001b2514bb620;
T_1 ;
%vpi_call 2 13 "$dumpfile", "distance_display_led.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001b2514bb620 {0 0 0};
%pushi/vec4 0, 0, 32;
%store/vec4 v000001b2514bbef0_0, 0, 32;
T_1.0 ; Top of for-loop
%load/vec4 v000001b2514bbef0_0;
%cmpi/s 400, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_1.1, 5;
%load/vec4 v000001b2514bbef0_0;
%pad/s 9;
%store/vec4 v000001b2514bbe50_0, 0, 9;
%delay 10, 0;
%vpi_call 2 20 "$display", "Distance: %3d cm => LEDs: %b", v000001b2514bbe50_0, v000001b2515d8150_0 {0 0 0};
T_1.2 ; for-loop step statement
%load/vec4 v000001b2514bbef0_0;
%addi 10, 0, 32;
%store/vec4 v000001b2514bbef0_0, 0, 32;
%jmp T_1.0;
T_1.1 ; for-loop exit label
%vpi_call 2 23 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb_distance_display_led.v";
"distance_display_led.v";

26
Semaine_1/Capteur_recule_bidirectionel/Distance_display_led/tb_distance_display_led.v Normal file
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module tb_distance_display_led;
reg [8:0] distance;
wire [5:0] leds;
distance_display_led uut (
.distance(distance),
.leds(leds)
);
integer i;
initial begin
$dumpfile("distance_display_led.vcd");
$dumpvars(0, tb_distance_display_led);
// Test de la conversion de distance en LED
for (i = 0; i <= 380; i = i + 10) begin
distance = i;
#10;
$display("Distance: %3d cm => LEDs: %b", distance, leds);
end
$finish;
end
endmodule

73
Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/tb_ultrasonic_fpga.v Normal file
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`timescale 1ns/1ps
module tb_ultrasonic_fpga;
reg clk = 0;
reg rst = 1;
reg start = 0;
reg echo = 0;
wire trig_out;
wire [8:0] distance;
time t_start, t_end;
// Clock 27MHz => periode = 37ns
always #18 clk = ~clk;
ultrasonic_fpga uut (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig_out(trig_out),
.distance(distance)
);
initial begin
$dumpfile("ultrasonic.vcd");
$dumpvars(0, tb_ultrasonic_fpga);
// Reset
#100;
rst = 0;
// Start
#100;
start = 1;
#40;
start = 0;
wait (trig_out == 1);
t_start = $time;
// Attendre qu'il redescende
wait (trig_out == 0);
t_end = $time;
$display("Trig HIGH duration: %0dns", t_end - t_start);
if ((t_end - t_start) >= 9500 && (t_end - t_start) <= 10500) begin
$display("Trigger signal is high for 10us.");
#10;
echo = 1;
#5800;// Echo dure 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
echo = 0;
end else begin
$display("Trigger signal is NOT high for 10us.");
end
#500;
// Affiche la distance
if (distance > 0) begin
$display("Distance measured: %d cm", distance);
end else begin
$display("No distance measured.");
end
$finish;
end
endmodule

114
Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v Normal file
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module ultrasonic_fpga #(
parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
)(
input wire clk,
input wire start,
inout wire sig, // Broche bidirectionnelle vers le capteur
output reg [15:0] distance, // Distance mesurée en cm
output reg [2:0] state = IDLE
);
reg [15:0] trig_counter;
reg [31:0] echo_counter;
reg sig_out;
reg sig_dir; // 1: output, 0: input
assign sig = sig_dir ? sig_out : 1'bz;
wire sig_in = sig;
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
DONE = 3'd5,
WAIT_NEXT = 3'd6;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1_000_000;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
reg [31:0] wait_counter;
always @(posedge clk) begin
case (state)
IDLE: begin
sig_out <= 0;
sig_dir <= 1;
distance <= 0;
if (start) begin
state <= TRIG_HIGH;
trig_counter <= 0;
end
end
TRIG_HIGH: begin
sig_out <= 1;
sig_dir <= 1;
if (trig_counter < TRIG_PULSE_CYCLES) begin
trig_counter <= trig_counter + 1;
end else begin
trig_counter <= 0;
state <= TRIG_LOW;
end
end
TRIG_LOW: begin
sig_out <= 0;
sig_dir <= 0; // Mettre en entrée
state <= WAIT_ECHO;
end
WAIT_ECHO: begin
if (sig_in) begin
echo_counter <= 0;
state <= MEASURE_ECHO;
end else if (echo_counter >= TIMEOUT_CYCLES) begin
distance <= 0;
state <= DONE;
end else begin
echo_counter <= echo_counter + 1;
end
end
MEASURE_ECHO: begin
if (sig_in) begin
if (echo_counter < TIMEOUT_CYCLES) begin
echo_counter <= echo_counter + 1;
end else begin
distance <= 0;
state <= DONE;
end
end else begin
distance <= (echo_counter * 1000) / DIST_DIVISOR;
state <= DONE;
end
end
DONE: begin
if (start) begin
wait_counter <= 0;
state <= WAIT_NEXT;
end else begin
state <= IDLE;
end
end
WAIT_NEXT: begin
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= TRIG_HIGH;
end
end
endcase
end
endmodule

27
Semaine_1/Capteur_recule_bidirectionel/distance_ws2812_display/distance_ws2812_display.v Normal file
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module distance_ws2812_display(
input wire clk,
input wire [8:0] distance, // distance mesurer
output wire ws2812_dout // broche de données pour la LED WS2812
);
reg [23:0] led_color; // couleur à envoyer à la LED (format RGB)
always @(posedge clk) begin
// Mapper la distance sur une couleur
if (distance < 100) begin
led_color <= 24'hFF0000; // Rouge (proche)
end else if (distance < 200) begin
led_color <= 24'hFFFF00; // Jaune (distance moyenne)
end else begin
led_color <= 24'h00FF00; // Vert (très loin)
end
end
// Instance du module de transmission pour WS2812
ws2812_driver ws2812_inst (
.clk(clk),
.color(led_color),
.ws2812_dout(ws2812_dout)
);
endmodule

441
Semaine_1/Capteur_recule_bidirectionel/distance_ws2812_display/distance_ws2812_display.vcd Normal file
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$date
Wed Apr 16 16:42:16 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb_distance_ws2812_display $end
$var wire 1 ! ws2812_dout $end
$var reg 1 " clk $end
$var reg 9 # distance [8:0] $end
$var integer 32 $ i [31:0] $end
$scope module uut $end
$var wire 1 " clk $end
$var wire 9 % distance [8:0] $end
$var wire 1 ! ws2812_dout $end
$var reg 24 & led_color [23:0] $end
$scope module ws2812_inst $end
$var wire 1 " clk $end
$var wire 24 ' color [23:0] $end
$var reg 8 ( bit_count [7:0] $end
$var reg 24 ) shift_reg [23:0] $end
$var reg 1 ! ws2812_dout $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
bx )
bx (
bx '
bx &
b0 %
b0 $
b0 #
0"
x!
$end
#5
b0 (
bx0 )
b111111110000000000000000 &
b111111110000000000000000 '
1"
#10
0"
b1010 #
b1010 %
b1010 $
#15
b1 (
0!
b111111110000000000000000 )
1"
#20
0"
b10100 #
b10100 %
b10100 $
#25
b10 (
b111111100000000000000000 )
1!
1"
#30
0"
b11110 #
b11110 %
b11110 $
#35
b11 (
b111111000000000000000000 )
1"
#40
0"
b101000 #
b101000 %
b101000 $
#45
b100 (
b111110000000000000000000 )
1"
#50
0"
b110010 #
b110010 %
b110010 $
#55
b101 (
b111100000000000000000000 )
1"
#60
0"
b111100 #
b111100 %
b111100 $
#65
b110 (
b111000000000000000000000 )
1"
#70
0"
b1000110 #
b1000110 %
b1000110 $
#75
b111 (
b110000000000000000000000 )
1"
#80
0"
b1010000 #
b1010000 %
b1010000 $
#85
b1000 (
b100000000000000000000000 )
1"
#90
0"
b1011010 #
b1011010 %
b1011010 $
#95
b1001 (
b0 )
1"
#100
0"
b1100100 #
b1100100 %
b1100100 $
#105
b1010 (
0!
b111111111111111100000000 &
b111111111111111100000000 '
1"
#110
0"
b1101110 #
b1101110 %
b1101110 $
#115
b1011 (
1"
#120
0"
b1111000 #
b1111000 %
b1111000 $
#125
b1100 (
1"
#130
0"
b10000010 #
b10000010 %
b10000010 $
#135
b1101 (
1"
#140
0"
b10001100 #
b10001100 %
b10001100 $
#145
b1110 (
1"
#150
0"
b10010110 #
b10010110 %
b10010110 $
#155
b1111 (
1"
#160
0"
b10100000 #
b10100000 %
b10100000 $
#165
b10000 (
1"
#170
0"
b10101010 #
b10101010 %
b10101010 $
#175
b10001 (
1"
#180
0"
b10110100 #
b10110100 %
b10110100 $
#185
b10010 (
1"
#190
0"
b10111110 #
b10111110 %
b10111110 $
#195
b10011 (
1"
#200
0"
b11001000 #
b11001000 %
b11001000 $
#205
b10100 (
b1111111100000000 &
b1111111100000000 '
1"
#210
0"
b11010010 #
b11010010 %
b11010010 $
#215
b10101 (
1"
#220
0"
b11011100 #
b11011100 %
b11011100 $
#225
b10110 (
1"
#230
0"
b11100110 #
b11100110 %
b11100110 $
#235
b10111 (
1"
#240
0"
b11110000 #
b11110000 %
b11110000 $
#245
b11000 (
1"
#250
0"
b11111010 #
b11111010 %
b11111010 $
#255
b0 (
1"
#260
0"
b100000100 #
b100000100 %
b100000100 $
#265
b1 (
b1111111100000000 )
1"
#270
0"
b100001110 #
b100001110 %
b100001110 $
#275
b10 (
b11111111000000000 )
1"
#280
0"
b100011000 #
b100011000 %
b100011000 $
#285
b11 (
b111111110000000000 )
1"
#290
0"
b100100010 #
b100100010 %
b100100010 $
#295
b100 (
b1111111100000000000 )
1"
#300
0"
b100101100 #
b100101100 %
b100101100 $
#305
b101 (
b11111111000000000000 )
1"
#310
0"
b100110110 #
b100110110 %
b100110110 $
#315
b110 (
b111111110000000000000 )
1"
#320
0"
b101000000 #
b101000000 %
b101000000 $
#325
b111 (
b1111111100000000000000 )
1"
#330
0"
b101001010 #
b101001010 %
b101001010 $
#335
b1000 (
b11111111000000000000000 )
1"
#340
0"
b101010100 #
b101010100 %
b101010100 $
#345
b1001 (
b111111110000000000000000 )
1"
#350
0"
b101011110 #
b101011110 %
b101011110 $
#355
b1010 (
b111111100000000000000000 )
1!
1"
#360
0"
b101101000 #
b101101000 %
b101101000 $
#365
b1011 (
b111111000000000000000000 )
1"
#370
0"
b101110010 #
b101110010 %
b101110010 $
#375
b1100 (
b111110000000000000000000 )
1"
#380
0"
b101111100 #
b101111100 %
b101111100 $
#385
b1101 (
b111100000000000000000000 )
1"
#390
0"
b110000110 $
#395
b1110 (
b111000000000000000000000 )
1"
#400
0"
#405
b1111 (
b110000000000000000000000 )
1"
#410
0"
#415
b10000 (
b100000000000000000000000 )
1"
#420
0"
#425
b10001 (
b0 )
1"
#430
0"
#435
b10010 (
0!
1"
#440
0"
#445
b10011 (
1"
#450
0"
#455
b10100 (
1"
#460
0"
#465
b10101 (
1"
#470
0"
#475
b10110 (
1"
#480
0"
#485
b10111 (
1"
#490

141
Semaine_1/Capteur_recule_bidirectionel/distance_ws2812_display/distance_ws2812_display.vvp Normal file
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@@ -0,0 +1,141 @@
#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_000002057b2ea610 .scope module, "tb_distance_ws2812_display" "tb_distance_ws2812_display" 2 2;
.timescale 0 0;
v000002057b2c69d0_0 .var "clk", 0 0;
v000002057b1dbfc0_0 .var "distance", 8 0;
v000002057b2f7a30_0 .var/i "i", 31 0;
v000002057b2f7c10_0 .net "ws2812_dout", 0 0, v000002057b2c66b0_0; 1 drivers
S_000002057b1db840 .scope module, "uut" "distance_ws2812_display" 2 9, 3 1 0, S_000002057b2ea610;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 9 "distance";
.port_info 2 /OUTPUT 1 "ws2812_dout";
v000002057b2c6750_0 .net "clk", 0 0, v000002057b2c69d0_0; 1 drivers
v000002057b2c67f0_0 .net "distance", 8 0, v000002057b1dbfc0_0; 1 drivers
v000002057b2c6890_0 .var "led_color", 23 0;
v000002057b2c6930_0 .net "ws2812_dout", 0 0, v000002057b2c66b0_0; alias, 1 drivers
S_000002057b1db9d0 .scope module, "ws2812_inst" "ws2812_driver" 3 21, 4 1 0, S_000002057b1db840;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 24 "color";
.port_info 2 /OUTPUT 1 "ws2812_dout";
v000002057b1dbb60_0 .var "bit_count", 7 0;
v000002057b2fba40_0 .net "clk", 0 0, v000002057b2c69d0_0; alias, 1 drivers
v000002057b2ea7a0_0 .net "color", 23 0, v000002057b2c6890_0; 1 drivers
v000002057b2c6610_0 .var "shift_reg", 23 0;
v000002057b2c66b0_0 .var "ws2812_dout", 0 0;
E_000002057b2e9430 .event posedge, v000002057b2fba40_0;
.scope S_000002057b1db9d0;
T_0 ;
%wait E_000002057b2e9430;
%load/vec4 v000002057b1dbb60_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.0, 4;
%load/vec4 v000002057b2ea7a0_0;
%assign/vec4 v000002057b2c6610_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000002057b2c66b0_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v000002057b2c6610_0;
%parti/s 1, 23, 6;
%assign/vec4 v000002057b2c66b0_0, 0;
%load/vec4 v000002057b2c6610_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v000002057b2c6610_0, 0;
T_0.1 ;
%load/vec4 v000002057b1dbb60_0;
%pad/u 32;
%cmpi/u 24, 0, 32;
%jmp/0xz T_0.2, 5;
%load/vec4 v000002057b1dbb60_0;
%addi 1, 0, 8;
%assign/vec4 v000002057b1dbb60_0, 0;
%jmp T_0.3;
T_0.2 ;
%pushi/vec4 0, 0, 8;
%assign/vec4 v000002057b1dbb60_0, 0;
T_0.3 ;
%jmp T_0;
.thread T_0;
.scope S_000002057b1db840;
T_1 ;
%wait E_000002057b2e9430;
%load/vec4 v000002057b2c67f0_0;
%pad/u 32;
%cmpi/u 100, 0, 32;
%jmp/0xz T_1.0, 5;
%pushi/vec4 16711680, 0, 24;
%assign/vec4 v000002057b2c6890_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v000002057b2c67f0_0;
%pad/u 32;
%cmpi/u 200, 0, 32;
%jmp/0xz T_1.2, 5;
%pushi/vec4 16776960, 0, 24;
%assign/vec4 v000002057b2c6890_0, 0;
%jmp T_1.3;
T_1.2 ;
%pushi/vec4 65280, 0, 24;
%assign/vec4 v000002057b2c6890_0, 0;
T_1.3 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_000002057b2ea610;
T_2 ;
%delay 5, 0;
%load/vec4 v000002057b2c69d0_0;
%inv;
%store/vec4 v000002057b2c69d0_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_000002057b2ea610;
T_3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000002057b2c69d0_0, 0, 1;
%pushi/vec4 0, 0, 9;
%store/vec4 v000002057b1dbfc0_0, 0, 9;
%vpi_call 2 22 "$dumpfile", "distance_ws2812_display.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_000002057b2ea610 {0 0 0};
%pushi/vec4 0, 0, 32;
%store/vec4 v000002057b2f7a30_0, 0, 32;
T_3.0 ; Top of for-loop
%load/vec4 v000002057b2f7a30_0;
%cmpi/s 380, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_3.1, 5;
%load/vec4 v000002057b2f7a30_0;
%pad/s 9;
%store/vec4 v000002057b1dbfc0_0, 0, 9;
%delay 10, 0;
%vpi_call 2 29 "$display", "Distance: %3d cm => LEDs: %b", v000002057b1dbfc0_0, v000002057b2f7c10_0 {0 0 0};
T_3.2 ; for-loop step statement
%load/vec4 v000002057b2f7a30_0;
%addi 10, 0, 32;
%store/vec4 v000002057b2f7a30_0, 0, 32;
%jmp T_3.0;
T_3.1 ; for-loop exit label
%delay 100, 0;
%vpi_call 2 32 "$stop" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"tb_distance_ws2812_display.v";
"distance_ws2812_display.v";
"ws2812_driver.v";

34
Semaine_1/Capteur_recule_bidirectionel/distance_ws2812_display/tb_distance_ws2812_display.v Normal file
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// Testbench pour distance_ws2812_display
module tb_distance_ws2812_display;
reg clk;
reg [8:0] distance;
wire ws2812_dout;
// Instance du module à tester
distance_ws2812_display uut (
.clk(clk),
.distance(distance),
.ws2812_dout(ws2812_dout)
);
always #5 clk = ~clk;
integer i;
initial begin
// Initialiser les signaux
clk = 0;
distance = 0;
$dumpfile("distance_ws2812_display.vcd");
$dumpvars(0, tb_distance_ws2812_display);
// Test de la conversion de distance en LED
for (i = 0; i <= 380; i = i + 10) begin
distance = i;
#10;
$display("Distance: %3d cm => dout: %b", distance, ws2812_dout);
end
#100 $stop; // Arrêter la simulation après un certain temps
end
endmodule

27
Semaine_1/Capteur_recule_bidirectionel/distance_ws2812_display/ws2812_driver.v Normal file
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module ws2812_driver(
input wire clk,
input wire [23:0] color, // couleur RGB (8 bits par composant)
output reg ws2812_dout // broche de données vers la LED
);
reg [7:0] bit_count; // compteur de bits pour envoyer les données
reg [23:0] shift_reg; // registre pour envoyer la couleur
always @(posedge clk) begin
if (bit_count == 0) begin
shift_reg <= color; // Charger la couleur à transmettre
ws2812_dout <= 1'b0; // Commencer par envoyer un "0"
end else begin
// Envoyer chaque bit un à un en contrôlant la durée de l'impulsion
ws2812_dout <= shift_reg[23]; // Le bit le plus significatif
shift_reg <= shift_reg << 1; // Décalage des bits
end
// Incrémentation du compteur de bits
if (bit_count < 24)
bit_count <= bit_count + 1;
else
bit_count <= 0; // Réinitialiser pour envoyer la prochaine couleur
end
endmodule

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Semaine_1/Capteur_recule_bidirectionel/tb_top_ultrasonic_led.v Normal file
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`timescale 1ns/1ps
module tb_top_ultrasonic_led;
reg clk;
reg rst;
reg start;
reg echo;
wire trig;
wire [5:0] leds;
// Instance du module top
top_ultrasonic_led uut (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig(trig),
.leds(leds)
);
always #18.5 clk = ~clk;
initial begin
// Initialisation
$dumpfile("top_ultrasonic_led.vcd");
$dumpvars(0, tb_top_ultrasonic_led);
clk = 0;
rst = 1;
start = 0;
echo = 0;
#100;
rst = 0;
#50;
start = 1;
#20;
start = 0;
// Attente du signal trig
wait (trig == 1);
$display("TRIG HIGH at %t", $time);
wait (trig == 0);
$display("TRIG LOW at %t", $time);
repeat (500) @(posedge clk);
echo = 1;
#12000
echo = 0;
repeat (500) @(posedge clk);
$display("Leds allumer : %b", leds);
$finish;
end
endmodule

32
Semaine_1/Capteur_recule_bidirectionel/top_ultrasonic_led.v Normal file
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module top_ultrasonic_led (
input wire clk,
input wire start, // bouton de déclenchement
inout wire sig, // broche unique pour trigger + echo
output wire [5:0] leds // LEDs pour affichage distance
output wire ws2812_dout // broche de données pour la LED WS2812 (optionnel)
);
wire [8:0] distance;
// Module de mesure (version bidirectionnelle du capteur)
ultrasonic_fpga ultrasonic_inst (
.clk(clk),
.start(start),
.sig(sig),
.distance(distance)
);
// Module d'affichage LEDs
distance_display_led led_display_inst (
.distance(distance),
.leds(leds)
);
// Module d'affichage WS2812 (optionnel, si vous souhaitez utiliser une LED RGB)
distance_ws2812_display ws2812_display_inst (
.clk(clk),
.distance(distance),
.ws2812_dout(ws2812_dout)
);
endmodule

7911
Semaine_1/Capteur_recule_bidirectionel/top_ultrasonic_led.vcd Normal file
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335
Semaine_1/Capteur_recule_bidirectionel/top_ultrasonic_led_tb.vvp Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_0000016babb102e0 .scope module, "tb_top_ultrasonic_led" "tb_top_ultrasonic_led" 2 3;
.timescale -9 -12;
v0000016babb7abc0_0 .var "clk", 0 0;
v0000016babb7ada0_0 .var "echo", 0 0;
v0000016babb7a580_0 .net "leds", 5 0, v0000016babb0e8e0_0; 1 drivers
v0000016babb7a260_0 .var "rst", 0 0;
v0000016babb7a620_0 .var "start", 0 0;
v0000016babb7a760_0 .net "trig", 0 0, v0000016babb7a120_0; 1 drivers
E_0000016babb0c2a0 .event posedge, v0000016babb7a4e0_0;
E_0000016babb0c320 .event anyedge, v0000016babb7a120_0;
S_0000016babae6610 .scope module, "uut" "top_ultrasonic_led" 2 13, 3 1 0, S_0000016babb102e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "start";
.port_info 3 /INPUT 1 "echo";
.port_info 4 /OUTPUT 1 "trig";
.port_info 5 /OUTPUT 6 "leds";
v0000016babb7ab20_0 .net "clk", 0 0, v0000016babb7abc0_0; 1 drivers
v0000016babb7af80_0 .net "distance", 8 0, v0000016babb7a440_0; 1 drivers
v0000016babb7a6c0_0 .net "echo", 0 0, v0000016babb7ada0_0; 1 drivers
v0000016babb7a800_0 .net "leds", 5 0, v0000016babb0e8e0_0; alias, 1 drivers
v0000016babb7ac60_0 .net "rst", 0 0, v0000016babb7a260_0; 1 drivers
v0000016babb7a9e0_0 .net "start", 0 0, v0000016babb7a620_0; 1 drivers
v0000016babb7aa80_0 .net "trig", 0 0, v0000016babb7a120_0; alias, 1 drivers
S_0000016babae67a0 .scope module, "led_display_inst" "distance_display_led" 3 23, 4 1 0, S_0000016babae6610;
.timescale 0 0;
.port_info 0 /INPUT 9 "distance";
.port_info 1 /OUTPUT 6 "leds";
P_0000016babae6930 .param/l "LEVELS" 0 4 9, +C4<00000000000000000000000000000101>;
P_0000016babae6968 .param/l "MAX_DIST" 0 4 8, +C4<00000000000000000000000101011101>;
P_0000016babae69a0 .param/l "MIN_DIST" 0 4 7, +C4<00000000000000000000000000000010>;
P_0000016babae69d8 .param/l "PART_SIZE" 0 4 10, +C4<0000000000000000000000000001000101>;
v0000016babb0e7a0_0 .net "distance", 8 0, v0000016babb7a440_0; alias, 1 drivers
v0000016babb0e8e0_0 .var "leds", 5 0;
E_0000016babb1a860 .event anyedge, v0000016babb0e7a0_0;
S_0000016babb23200 .scope module, "ultrasonic_inst" "ultrasonic_fpga" 3 13, 5 1 0, S_0000016babae6610;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "start";
.port_info 3 /INPUT 1 "echo";
.port_info 4 /OUTPUT 1 "trig_out";
.port_info 5 /OUTPUT 9 "distance";
P_0000016babb23390 .param/l "CLK_FREQ" 0 5 2, +C4<00000001100110111111110011000000>;
P_0000016babb233c8 .param/l "DIST_DIVISOR" 1 5 20, +C4<00000000000000000000011000011110>;
P_0000016babb23400 .param/l "DONE" 1 5 16, +C4<00000000000000000000000000000100>;
P_0000016babb23438 .param/l "IDLE" 1 5 16, +C4<00000000000000000000000000000000>;
P_0000016babb23470 .param/l "MEASURE_ECHO" 1 5 16, +C4<00000000000000000000000000000011>;
P_0000016babb234a8 .param/l "TRIG" 1 5 16, +C4<00000000000000000000000000000001>;
P_0000016babb234e0 .param/l "TRIG_DURATION_CYCLES" 1 5 19, +C4<00000000000000000000000100001110>;
P_0000016babb23518 .param/l "WAIT_ECHO" 1 5 16, +C4<00000000000000000000000000000010>;
v0000016babb7a4e0_0 .net "clk", 0 0, v0000016babb7abc0_0; alias, 1 drivers
v0000016babb7a440_0 .var "distance", 8 0;
v0000016babb7a080_0 .net "echo", 0 0, v0000016babb7ada0_0; alias, 1 drivers
v0000016babb7aee0_0 .var "echo_counter", 15 0;
v0000016babb7a940_0 .net "rst", 0 0, v0000016babb7a260_0; alias, 1 drivers
v0000016babb7a8a0_0 .net "start", 0 0, v0000016babb7a620_0; alias, 1 drivers
v0000016babb7a1c0_0 .var "state", 2 0;
v0000016babb7a3a0_0 .var "trig_counter", 8 0;
v0000016babb7a120_0 .var "trig_out", 0 0;
E_0000016babb1a8e0 .event posedge, v0000016babb7a940_0, v0000016babb7a4e0_0;
.scope S_0000016babb23200;
T_0 ;
%wait E_0000016babb1a8e0;
%load/vec4 v0000016babb7a940_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a440_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0000016babb7a1c0_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%jmp T_0.7;
T_0.2 ;
%load/vec4 v0000016babb7a8a0_0;
%flag_set/vec4 8;
%jmp/0xz T_0.8, 8;
%pushi/vec4 1, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.8 ;
%jmp T_0.7;
T_0.3 ;
%load/vec4 v0000016babb7a3a0_0;
%pad/u 32;
%cmpi/u 270, 0, 32;
%jmp/0xz T_0.10, 5;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%load/vec4 v0000016babb7a3a0_0;
%addi 1, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000016babb7a120_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0000016babb7a3a0_0, 0;
%pushi/vec4 2, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.11 ;
%jmp T_0.7;
T_0.4 ;
%load/vec4 v0000016babb7a080_0;
%flag_set/vec4 8;
%jmp/0xz T_0.12, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%pushi/vec4 3, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.12 ;
%jmp T_0.7;
T_0.5 ;
%load/vec4 v0000016babb7a080_0;
%flag_set/vec4 8;
%jmp/0xz T_0.14, 8;
%load/vec4 v0000016babb7aee0_0;
%addi 1, 0, 16;
%assign/vec4 v0000016babb7aee0_0, 0;
%jmp T_0.15;
T_0.14 ;
%load/vec4 v0000016babb7aee0_0;
%pad/u 32;
%muli 1000, 0, 32;
%pushi/vec4 1566, 0, 32;
%div;
%pad/u 9;
%assign/vec4 v0000016babb7a440_0, 0;
%pushi/vec4 4, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
T_0.15 ;
%jmp T_0.7;
T_0.6 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0000016babb7a1c0_0, 0;
%jmp T_0.7;
T_0.7 ;
%pop/vec4 1;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0000016babae67a0;
T_1 ;
%wait E_0000016babb1a860;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 2, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.0, 5;
%pushi/vec4 63, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 71, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.2, 5;
%pushi/vec4 62, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.3;
T_1.2 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 140, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.4, 5;
%pushi/vec4 60, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.5;
T_1.4 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 209, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.6, 5;
%pushi/vec4 56, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.7;
T_1.6 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 278, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.8, 5;
%pushi/vec4 48, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.9;
T_1.8 ;
%load/vec4 v0000016babb0e7a0_0;
%pad/u 34;
%cmpi/u 347, 0, 34;
%flag_or 5, 4;
%jmp/0xz T_1.10, 5;
%pushi/vec4 32, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
%jmp T_1.11;
T_1.10 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v0000016babb0e8e0_0, 0, 6;
T_1.11 ;
T_1.9 ;
T_1.7 ;
T_1.5 ;
T_1.3 ;
T_1.1 ;
%jmp T_1;
.thread T_1, $push;
.scope S_0000016babb102e0;
T_2 ;
%delay 18500, 0;
%load/vec4 v0000016babb7abc0_0;
%inv;
%store/vec4 v0000016babb7abc0_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_0000016babb102e0;
T_3 ;
%vpi_call 2 26 "$dumpfile", "top_ultrasonic_led.vcd" {0 0 0};
%vpi_call 2 27 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000016babb102e0 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7abc0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7a260_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%delay 100000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a260_0, 0, 1;
%delay 50000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
%delay 20000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7a620_0, 0, 1;
T_3.0 ;
%load/vec4 v0000016babb7a760_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.1, 6;
%wait E_0000016babb0c320;
%jmp T_3.0;
T_3.1 ;
%vpi_call 2 44 "$display", "TRIG HIGH at %t", $time {0 0 0};
T_3.2 ;
%load/vec4 v0000016babb7a760_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_3.3, 6;
%wait E_0000016babb0c320;
%jmp T_3.2;
T_3.3 ;
%vpi_call 2 46 "$display", "TRIG LOW at %t", $time {0 0 0};
%pushi/vec4 500, 0, 32;
T_3.4 %dup/vec4;
%cmpi/s 0, 0, 32;
%jmp/1xz T_3.5, 5;
%jmp/1 T_3.5, 4;
%subi 1, 0, 32;
%wait E_0000016babb0c2a0;
%jmp T_3.4;
T_3.5 ;
%pop/vec4 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%delay 18000000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000016babb7ada0_0, 0, 1;
%pushi/vec4 500, 0, 32;
T_3.6 %dup/vec4;
%cmpi/s 0, 0, 32;
%jmp/1xz T_3.7, 5;
%jmp/1 T_3.7, 4;
%subi 1, 0, 32;
%wait E_0000016babb0c2a0;
%jmp T_3.6;
T_3.7 ;
%pop/vec4 1;
%vpi_call 2 56 "$display", "LEDs allumer : %b", v0000016babb7a580_0 {0 0 0};
%vpi_call 2 58 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"tb_top_ultrasonic_led.v";
"top_ultrasonic_led.v";
"Distance_display_led/distance_display_led.v";
"Ultrasonic/ultrasonic_fpga.v";

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import serial
import time
# Ouvre le port série (à adapter si nécessaire)
ser = serial.Serial('COM6', 115200, timeout=0.5) # timeout non bloquant
print("Entrez un chiffre entre 0 et 5 pour toggler une LED.")
try:
while True:
user_input = input("> ")
if user_input.isdigit() and 0 <= int(user_input) <= 64:
value = int(user_input)
ser.write(bytes([value])) # envoie en binaire brut
print(f"Envoyé : {value} -> {value:08b}")
# Lecture de la réponse UART (1 octet)
response = ser.read(1)
if response:
led_state = response[0]
print(f"État reçu du FPGA : {led_state:08b}")
else:
print("⚠️ Aucune réponse reçue.")
else:
print("Veuillez entrer un chiffre entre 0 et 63.")
except KeyboardInterrupt:
print("\nFermeture.")
finally:
ser.close()

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import serial
import time
ser = serial.Serial('COM6', 115200)
ser.timeout = 1
# Boucle pour lire les données du port série
while True:
if ser.in_waiting > 0:
data = ser.read(1)
distance = int.from_bytes(data, byteorder='little')
print(f'Distance reçue : {distance} cm')
ser.close()

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69
Semaine_1/UART/tb_top_uart_rx_tx.v Normal file
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`timescale 1ns / 1ps
module tb_top_uart_rx_tx;
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115200;
// Signaux
reg clk = 0;
reg start = 0;
reg [7:0] data_in = 0;
wire [7:0] data_out;
wire valid;
wire tx;
wire rx; // On connecte tx directement à rx pour le test
// Instance du module à tester
top_uart_rx_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uut (
.clk(clk),
.start(start),
.data_in(data_in),
.rx(rx),
.data_out(data_out),
.valid(valid),
.tx(tx)
);
// Boucle le tx sur rx
assign rx = tx;
// Clock à 50 MHz (20 ns période)
always #10 clk = ~clk;
// Simulation principale
initial begin
$display("Début de la simulation");
$dumpfile("uart_loopback.vcd"); // Pour GTKWave
$dumpvars(0, tb_top_uart_rx_tx);
// Attendre un peu
#(20 * 10);
// Envoi d'une valeur
data_in = 8'hA5; // Exemple de data
start = 1;
#20;
start = 0;
// Attendre la réception (valeur valid = 1)
wait(valid == 1);
// Affichage des résultats
$display("Data envoyee : 0x%h", data_in);
$display("Data recue : 0x%h", data_out);
if (data_out == data_in)
$display("Test reussi !");
else
$display("Test echoue...");
// Fin de simulation
#(20 * 10);
$finish;
end
endmodule

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`timescale 1ns / 1ps
module tb_uart_rx;
reg clk = 0;
reg rx = 1;
wire [7:0] data;
wire valid;
wire ready;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ;
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx(rx),
.data(data),
.valid(valid),
.ready(ready)
);
always #(CLK_PERIOD_NS/2) clk = ~clk;
task send_bit(input reg b);
begin
rx <= b;
#(BIT_PERIOD * CLK_PERIOD_NS);
end
endtask
integer i;
task send_byte(input [7:0] byte);
begin
send_bit(0);
for (i = 0; i < 8; i = i + 1)
send_bit(byte[i]);
send_bit(1);
#(BIT_PERIOD * CLK_PERIOD_NS);
end
endtask
initial begin
$display("Start UART RX test");
#100;
send_byte(8'b01010101);
#(10 * BIT_PERIOD * CLK_PERIOD_NS);
if (valid && data == 8'b01010101)
$display("Test ok : data = %b", data);
else
$display("Test pas ok : data = %b, valid = %b", data, valid);
$finish;
end
endmodule

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`timescale 1ns/1ps
module tb_uart_tx;
reg clk = 0;
reg start = 0;
reg [7:0] data = 8'h00;
wire tx;
wire busy;
always #18.5 clk = ~clk;
uart_tx #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200)
)tx_instance (
.clk(clk),
.start(start),
.data(data),
.tx(tx),
.busy(busy)
);
initial begin
$dumpfile("uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
#100;
data <= 8'hA5; // 10100101 0xA5
start <= 1;
#37 start <= 0;
// Attendre
wait (busy == 0);
#1000;
data <= 8'h3C; // 00111100 0x3C
start <= 1;
#37 start <= 0;
wait (busy == 0);
#1000;
$stop;
end
endmodule

61
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module top_led_uart(
input wire clk,
input wire rx,
output wire tx,
output reg [5:0] leds
);
wire [7:0] data_out;
wire valid;
reg start_tx = 0;
reg [7:0] data_in = 0;
top_uart_rx_tx uart (
.clk(clk),
.start(start_tx),
.data_in(data_in),
.rx(rx),
.data_out(data_out),
.valid(valid),
.tx(tx)
);
reg [1:0] state = 0;
localparam IDLE = 2'd0;
localparam TOGGLE = 2'd1;
localparam SEND_BACK = 2'd2;
always @(posedge clk) begin
case (state)
INIT: begin
leds <= 6'b000000;
start_tx <= 0;
if (valid) begin
leds <= data_out[5:0];
state <= SEND_BACK;
end
end
IDLE: begin
start_tx <= 0;
if (valid) begin
leds <= data_out[5:0];
state <= SEND_BACK;
end
end
SEND_BACK: begin
data_in <= data_out;
start_tx <= 1;
state <= TOGGLE;
end
TOGGLE: begin
start_tx <= 0;
state <= IDLE;
end
endcase
end
endmodule

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Semaine_1/UART/top_uart_rx_tx.v Normal file
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module top_uart_rx_tx(
input wire clk,
input wire start, // Commencer l'ecriture
input wire [7:0] data_in,
input wire rx,
output wire [7:0] data_out,
output wire valid, // Si 1 alors on peut lire
output wire tx
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) tx_instance (
.clk(clk),
.start(start),
.data(data_in),
.tx(tx)
);
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx(rx),
.data(data_out),
.valid(valid)
);
endmodule

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module uart_rx (
input wire clk,
input wire rx, // signal reçues
output reg [7:0] data, // Données decoder
output reg valid = 0, // Indicateur de données valides
output reg ready = 1 // Indicateur de réception prête
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam STOP = 2'b11;
reg [1:0] state = IDLE;
reg [3:0] bit_index;
reg [15:0] clk_count;
reg [7:0] rx_data = 0;
always @(posedge clk) begin
case (state)
IDLE: begin
ready <= 1;
if (!rx) begin // start bit (0)
state <= START;
clk_count <= 0;
bit_index <= 0;
valid <= 0;
ready <= 0;
end
end
START: begin
if (clk_count < (BIT_PERIOD / 2) - 1) begin // Attendre juste 0.5 bit
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
state <= DATA;
end
end
DATA: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
rx_data[bit_index] <= rx; // Recevoir les données (8 bits)
bit_index <= bit_index + 1;
if (bit_index == 7) begin
state <= STOP; // Passer à l'état d'arrêt
end
end
end
STOP: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
state <= IDLE;
data <= rx_data;
valid <= 1;
ready <= 1;
end
end
endcase
end
endmodule

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Semaine_1/UART/uart_tx.v Normal file
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module uart_tx(
input wire clk,
input wire start,
input wire [7:0] data,
output reg tx = 1,
output reg busy = 0
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam STOP = 2'b11;
reg [1:0] state = IDLE;
reg [3:0] bit_index = 0;
reg [15:0] clk_count = 0;
reg [7:0] tx_data = 0;
always @(posedge clk) begin
case(state)
IDLE: begin
tx <= 1;
if (start) begin
tx_data <= data;
bit_index <= 0;
clk_count <= 0;
busy <= 1;
state <= START;
end
end
START: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
tx <= 0;
end else begin
state <= DATA;
clk_count <= 0;
end
end
DATA: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else if (bit_index < 8) begin
tx <= tx_data[bit_index];
bit_index <= bit_index + 1;
clk_count <= 0;
end else begin
state <= STOP;
end
end
STOP: begin
tx <= 1;
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
busy <= 0;
state <= IDLE;
end
end
endcase
end
endmodule

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module uart_tx(
input wire clk,
input wire start, // Signal de démarrage de la transmission
input wire [7:0] data, // Données à transmettre
output reg tx, // Sortie de transmission
output reg busy // Indicateur de transmission en cours
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
reg [3:0] bit_index;
reg [15:0] clk_count;
reg [7:0] tx_data = 0;
initial begin
tx = 1; // État idle (1)
busy = 0; // Pas de transmission en cours
end
always @(posedge clk) begin
if (start && !busy) begin
busy <= 1; // Démarrer la transmission
bit_index <= 0; // Réinitialiser l'index du bit
clk_count <= 0; // Réinitialiser le compteur d'horloge
tx_data <= data;
tx <= 1; // État idle (1)
end else if (busy) begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
if (bit_index == 0) begin
tx <= 0; // Start bit (0)
end else if (bit_index < 9) begin
tx <= tx_data[bit_index - 1]; // Transmettre les données (8 bits)
end else if (bit_index == 9) begin
tx <= 1; // Stop bit (1)
end else begin
busy <= 0; // Fin de la transmission
end
bit_index <= bit_index + 1; // Passer au bit suivant
end
end else begin
tx <= 1; // État idle (1)
end
end
endmodule

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69
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`timescale 1ns / 1ps
module tb_top_uart_rx_tx;
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115200;
// Signaux
reg clk = 0;
reg start = 0;
reg [7:0] data_in = 0;
wire [7:0] data_out;
wire valid;
wire tx;
wire rx; // On connecte tx directement à rx pour le test
// Instance du module à tester
top_uart_rx_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) uut (
.clk(clk),
.start(start),
.data_in(data_in),
.rx(rx),
.data_out(data_out),
.valid(valid),
.tx(tx)
);
// Boucle le tx sur rx
assign rx = tx;
// Clock à 50 MHz (20 ns période)
always #10 clk = ~clk;
// Simulation principale
initial begin
$display("Début de la simulation");
$dumpfile("uart_loopback.vcd"); // Pour GTKWave
$dumpvars(0, tb_top_uart_rx_tx);
// Attendre un peu
#(20 * 10);
// Envoi d'une valeur
data_in = 8'hA5; // Exemple de data
start = 1;
#20;
start = 0;
// Attendre la réception (valeur valid = 1)
wait(valid == 1);
// Affichage des résultats
$display("Data envoyee : 0x%h", data_in);
$display("Data recue : 0x%h", data_out);
if (data_out == data_in)
$display("Test reussi !");
else
$display("Test echoue...");
// Fin de simulation
#(20 * 10);
$finish;
end
endmodule

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`timescale 1ns / 1ps
module tb_uart_rx;
reg clk = 0;
reg rx = 1;
wire [7:0] data;
wire valid;
wire ready;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ;
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx(rx),
.data(data),
.valid(valid),
.ready(ready)
);
always #(CLK_PERIOD_NS/2) clk = ~clk;
task send_bit(input reg b);
begin
rx <= b;
#(BIT_PERIOD * CLK_PERIOD_NS);
end
endtask
integer i;
task send_byte(input [7:0] byte);
begin
send_bit(0);
for (i = 0; i < 8; i = i + 1)
send_bit(byte[i]);
send_bit(1);
#(BIT_PERIOD * CLK_PERIOD_NS);
end
endtask
initial begin
$display("Start UART RX test");
#100;
send_byte(8'b01010101);
#(10 * BIT_PERIOD * CLK_PERIOD_NS);
if (valid && data == 8'b01010101)
$display("Test ok : data = %b", data);
else
$display("Test pas ok : data = %b, valid = %b", data, valid);
$finish;
end
endmodule

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Semaine_1/UARTV2/tb_uart_tx.v Normal file
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`timescale 1ns/1ps
module tb_uart_tx;
reg clk = 0;
reg start = 0;
reg [7:0] data = 8'h00;
wire tx;
wire busy;
always #18.5 clk = ~clk;
uart_tx #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200)
)tx_instance (
.clk(clk),
.start(start),
.data(data),
.tx(tx),
.busy(busy)
);
initial begin
$dumpfile("uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
#100;
data <= 8'hA5; // 10100101 0xA5
start <= 1;
#37 start <= 0;
// Attendre
wait (busy == 0);
#1000;
data <= 8'h3C; // 00111100 0x3C
start <= 1;
#37 start <= 0;
wait (busy == 0);
#1000;
$stop;
end
endmodule

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Semaine_1/UARTV2/top_led_uart.v Normal file
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module top_led_uart(
input wire clk,
input wire rx,
output wire tx,
output reg [5:0] leds
);
wire [7:0] data_out;
wire valid;
reg start_tx = 0;
reg [7:0] data_in = 0;
top_uart_rx_tx uart (
.clk(clk),
.start(start_tx),
.data_in(data_in),
.rx(rx),
.data_out(data_out),
.valid(valid),
.tx(tx)
);
reg [1:0] state = 0;
localparam IDLE = 2'd0;
localparam TOGGLE = 2'd1;
localparam SEND_BACK = 2'd2;
always @(posedge clk) begin
case (state)
INIT: begin
leds <= 6'b000000;
start_tx <= 0;
if (valid) begin
leds <= data_out[5:0];
state <= SEND_BACK;
end
end
IDLE: begin
start_tx <= 0;
if (valid) begin
leds <= data_out[5:0];
state <= SEND_BACK;
end
end
SEND_BACK: begin
data_in <= data_out;
start_tx <= 1;
state <= TOGGLE;
end
TOGGLE: begin
start_tx <= 0;
state <= IDLE;
end
endcase
end
endmodule

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Semaine_1/UARTV2/top_uart_rx_tx.v Normal file
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module uart_top(
input clk,
input rst,
input uart_rx,
output uart_tx
);
parameter CLK_FRE = 27_000_000; // Mhz
parameter UART_FRE = 115200; // Baud
localparam IDLE = 0;
localparam SEND = 1; // send
localparam WAIT = 2; // wait 1 second and send uart received data
reg[7:0] tx_data;
reg[7:0] tx_str;
reg tx_data_valid;
wire tx_data_ready;
reg[7:0] tx_cnt;
wire[7:0] rx_data;
wire rx_data_valid;
wire rx_data_ready;
reg[31:0] wait_cnt;
reg[3:0] state;
wire rst_p = rst;
assign rx_data_ready = 1'b1; //always can receive data,
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
begin
wait_cnt <= 32'd0;
tx_data <= 8'd0;
state <= IDLE;
tx_cnt <= 8'd0;
tx_data_valid <= 1'b0;
end
else
case(state)
IDLE:begin
state <= SEND;
end
SEND:begin
wait_cnt <= 32'd0;
tx_data <= tx_str;
if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < DATA_NUM - 1)//Send 12 bytes data
begin
tx_cnt <= tx_cnt + 8'd1; //Send data counter
end
else if(tx_data_valid && tx_data_ready)//last byte sent is complete
begin
tx_cnt <= 8'd0;
tx_data_valid <= 1'b0;
state <= WAIT;
end
else if(~tx_data_valid)
begin
tx_data_valid <= 1'b1;
end
end
WAIT:begin
wait_cnt <= wait_cnt + 32'd1;
if(rx_data_valid == 1'b1)
begin
tx_data_valid <= 1'b1;
tx_data <= rx_data; // send uart received data
end
else if(tx_data_valid && tx_data_ready)
begin
tx_data_valid <= 1'b0;
end
else if(wait_cnt >= CLK_FRE * 1000_000) // wait for 1 second
state <= SEND;
end
default:
state <= IDLE;
endcase
end
always@(*)
tx_str <= send_data[(DATA_NUM - 1 - tx_cnt) * 8 +: 8];
uart_rx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(UART_FRE)
) uart_rx_inst
(
.clk (clk),
.rst_p (rst_p),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_data_ready (rx_data_ready),
.rx_pin (uart_rx)
);
uart_tx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(UART_FRE)
) uart_tx_inst
(
.clk (clk),
.rst_p (rst_p),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_data_ready (tx_data_ready),
.tx_pin (uart_tx)
);
endmodule

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module uart_rx #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
)(
input clk, //clock input
input rst_p, //asynchronous reset input, high active
input rx_data_ready, //data receiver module ready
input rx_pin, //serial data input
output reg[7:0] rx_data, //received serial data
output reg rx_data_valid //received serial data is valid
);
localparam CYCLE = CLK_FREQ * / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2; //start bit
localparam S_REC_BYTE = 3; //data bits
localparam S_STOP = 4; //stop bit
localparam S_DATA = 5;
reg[2:0] state;
reg[2:0] next_state;
reg rx_d0; //delay 1 clock for rx_pin
reg rx_d1; //delay 1 clock for rx_d0
wire rx_negedge; //negedge of rx_pin
reg[7:0] rx_bits; //temporary storage of received data
reg[15:0] cycle_cnt; //baud counter
reg[2:0] bit_cnt; //bit counter
assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
always@(posedge clk or negedge rst_p) // Filtrage du signial
begin
if(rst_p == 1'b1)begin
rx_d0 <= 1'b0;
rx_d1 <= 1'b0;
end else begin
rx_d0 <= rx_pin;
rx_d1 <= rx_d0;
end
end
always@(posedge clk or negedge rst_p)begin // Compteur d'etat
if(rst_p == 1'b1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)begin
case(state)
S_IDLE:
if(rx_negedge) // Detection du start bit
next_state = S_START;
else
next_state = S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1) //one data cycle
next_state = S_REC_BYTE;
else
next_state = S_START;
S_REC_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
next_state = S_STOP;
else
next_state = S_REC_BYTE;
S_STOP:
if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
next_state = S_DATA;
else
next_state = S_STOP;
S_DATA:
if(rx_data_ready) //data receive complete
next_state = S_IDLE;
else
next_state = S_DATA;
default:
next_state = S_IDLE;
endcase
end
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
rx_data_valid <= 1'b0;
else if(state == S_STOP && next_state != state)
rx_data_valid <= 1'b1;
else if(state == S_DATA && rx_data_ready)
rx_data_valid <= 1'b0;
end
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
rx_data <= 8'd0;
else if(state == S_STOP && next_state != state)
rx_data <= rx_bits;//latch received data
end
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
begin
bit_cnt <= 3'd0;
end
else if(state == S_REC_BYTE)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
//receive serial data bit data
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
rx_bits <= 8'd0;
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
rx_bits[bit_cnt] <= rx_pin;
else
rx_bits <= rx_bits;
end
endmodule

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module uart_tx #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_p,
input wire[7:0] data,
input wire tx_data_valid,
output wire tx,
output reg tx_data_ready
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'd0;
localparam START = 2'd1;
localparam DATA = 2'd2;
localparam STOP = 2'd3;
reg [1:0] state = IDLE;
reg [1:0] next_state;
reg [15:0] cycle_cnt; //baud counter
reg [3:0] bit_index = 0;
reg [15:0] clk_count = 0;
reg [7:0] tx_data = 0;
reg tx_reg;
assign tx = tx_reg;
always@(posedge clk or posedge rst_p)begin // Avance d'etat
if(rst_p == 1'b1)
state <= IDLE;
else
state <= next_state;
end
always@(*) begin
case(state)
IDLE:
if(tx_data_valid == 1'b1)
next_state = START;
else
next_state = IDLE;
START:
if(cycle_cnt == CYCLE - 1)
next_state = DATA;
else
next_state = START;
DATA:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state = STOP;
else
next_state = DATA;
STOP:
if(cycle_cnt == CYCLE - 1)
next_state = IDLE;
else
next_state = STOP;
default:
next_state = IDLE;
endcase
end
always@(posedge clk or posedge rst_p)begin // tx_data_ready block
if(rst_p == 1'b1)
begin
tx_data_ready <= 1'b0;
end
else if(state == IDLE)
if(tx_data_valid == 1'b1)
tx_data_ready <= 1'b0;
else
tx_data_ready <= 1'b1;
else if(state == STOP && cycle_cnt == CYCLE - 1)
tx_data_ready <= 1'b1;
end
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
if(rst_p == 1'b1)begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_data_valid == 1'b1)
tx_data_latch <= tx_data;
end
always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
if(rst_p == 1'b1)begin
bit_cnt <= 3'd0;
end else if(state == DATA)
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
else
bit_cnt <= 3'd0;
end
always@(posedge clk or posedge rst_p)begin // Cycle counter
if(rst_p == 1'b1)
cycle_cnt <= 16'd0;
else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or posedge rst_p)begin // tx state managment
if(rst_p == 1'b1)
tx_reg <= 1'b1;
else
case(state)
IDLE,STOP:
tx_reg <= 1'b1;
START:
tx_reg <= 1'b0;
DATA:
tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
default:
tx_reg <= 1'b1;
endcase
end
endmodule

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module top_ultrason_uart(
input wire clk,
input wire start,
inout wire sig,
output wire tx
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
// Paramètres pour le capteur à ultrasons
wire [15:0] distance;
wire [2:0] state_sensor;
// Signaux pour l'UART TX
reg [15:0] tx_data;
reg tx_start = 0;
// Instance du capteur à ultrasons
ultrasonic_fpga #(
.CLK_FREQ(CLK_FREQ)
) sensor_inst (
.clk(clk),
.start(start),
.sig(sig),
.distance(distance),
.state(state_sensor)
);
// Instance de l'UART TX
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) tx_instance (
.clk(clk),
.start(tx_start),
.data(tx_data[7:0]),
.tx(tx)
);
reg [31:0] wait_counter;
reg [1:0] state;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
localparam START = 2'd0;
localparam WAIT = 2'd1;
always @(posedge clk) begin
case(state)
START:begin
if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
tx_data <= distance;
tx_start <= 1;
state <= WAIT;
end
end
WAIT:begin
tx_start <= 0;
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= START;
wait_counter <= 0;
end
end
endcase
end
endmodule