Init et début de réflexion sur le projet

Semaine_1/UARTV2/tb_uart_tx.v

@@ -0,0 +1,49 @@
+`timescale 1ns/1ps
+
+module tb_uart_tx;
+
+    reg clk = 0;
+    reg start = 0;
+    reg [7:0] data = 8'h00;
+    wire tx;
+    wire busy;
+
+    always #18.5 clk = ~clk;
+
+    uart_tx #(
+        .CLK_FREQ(27_000_000),
+        .BAUD_RATE(115_200)
+    )tx_instance (
+        .clk(clk),
+        .start(start),
+        .data(data),
+        .tx(tx),
+        .busy(busy)
+    );
+
+    initial begin
+        $dumpfile("uart_tx.vcd");
+        $dumpvars(0, tb_uart_tx);
+
+        #100;
+
+        data <= 8'hA5;   // 10100101 0xA5
+        start <= 1;
+        #37 start <= 0; 
+
+        // Attendre
+        wait (busy == 0);
+
+        #1000;
+
+        data <= 8'h3C;   // 00111100  0x3C
+        start <= 1;
+        #37 start <= 0;
+
+        wait (busy == 0);
+
+        #1000;
+        $stop;
+    end
+
+endmodule