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forked from tanchou/Verilog

Update clock frequency in fpga_wifi_led module to 57.857142 MHz

This commit is contained in:
Gamenight77
2025-05-29 13:25:53 +02:00
parent 0f14bf24a6
commit 3f3e4fcd6b

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@@ -8,7 +8,7 @@ module fpga_wifi_led (
// === PARAMÈTRES === // === PARAMÈTRES ===
localparam CLK_FREQ = 27_000_000; localparam CLK_FREQ = 57_857_142;
localparam BAUD_RATE = 500000; localparam BAUD_RATE = 500000;
localparam FIFO_SIZE = 8; localparam FIFO_SIZE = 8;