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Refactor DHT11 interface to support 16-bit temperature and humidity data, update checksum handling, and improve state machine logic

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Gamenight77
2025-05-27 13:34:59 +02:00
parent 286ba6b33c
commit 425cc8d00c
3 changed files with 71 additions and 95 deletions
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24
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -1,3 +1,4 @@
`default_nettype none
module dht11_interface #(
parameter CLK_FREQ = 27_000_000
)(
@@ -66,7 +67,6 @@ module dht11_interface #(
bit_index = 0;
raw_data = 0;
o_dht11_data_ready = 0;
o_dht11_error = 0;
end
// === FSM principale ===
@@ -90,7 +90,6 @@ module dht11_interface #(
o_busy <= 1;
state <= START;
o_dht11_data_ready <= 0;
o_dht11_error <= 0;
end
end
@@ -108,10 +107,10 @@ module dht11_interface #(
timer <= timer + 1;
if (sig_in == 0) begin
if (sig_in == 0 && timer > 1) begin
state <= RESPONSE_LOW;
timer <= 0;
state <= RESPONSE_LOW;
timer <= 0;
end
end
@@ -122,8 +121,8 @@ module dht11_interface #(
if (sig_in == 1) begin
timer <= 0;
state <= RESPONSE_HIGH;
timer <= 0;
state <= RESPONSE_HIGH;
end
end
@@ -142,26 +141,25 @@ module dht11_interface #(
READ_BITS_LOW: begin
o_state <= state;
timer <= timer + 1;
if (sig_in == 1) begin
timer <= 0;
state <= READ_BITS_HIGH;
timer <= 0;
state <= READ_BITS_HIGH;
end
end
READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
o_state <= state;
timer <= timer + 1;
if (sig_in == 0) begin
raw_data <= {raw_data[38:0], (timer > T_40US)};
timer <= 0;
bit_index <= bit_index + 1;
if (bit_index == 40) begin
if (bit_index == 39) begin
state <= DONE;
end else begin
state <= READ_BITS_LOW;