diff --git a/Semaine_6/DHT11/project.bat b/Semaine_6/DHT11/project.bat index c087898..987449a 100644 --- a/Semaine_6/DHT11/project.bat +++ b/Semaine_6/DHT11/project.bat @@ -1,5 +1,8 @@ @call c:\oss-cad-suite\environment.bat @echo off + +mkdir runs + if "%1"=="sim" call scripts\windows\simulate.bat if "%1"=="wave" call scripts\windows\gtkwave.bat if "%1"=="clean" call scripts\windows\clean.bat diff --git a/Semaine_6/DHT11/scripts/windows/gtkwave.bat b/Semaine_6/DHT11/scripts/windows/gtkwave.bat index c4180e0..0b86154 100644 --- a/Semaine_6/DHT11/scripts/windows/gtkwave.bat +++ b/Semaine_6/DHT11/scripts/windows/gtkwave.bat @@ -1,3 +1,3 @@ @echo off echo === Lancement de GTKWave === -gtkwave runs/wave.vcd +gtkwave runs/sim.vcd diff --git a/Semaine_6/DHT11/src/verilog/dht11_interface.v b/Semaine_6/DHT11/src/verilog/dht11_interface.v index c61fbc6..77d49ea 100644 --- a/Semaine_6/DHT11/src/verilog/dht11_interface.v +++ b/Semaine_6/DHT11/src/verilog/dht11_interface.v @@ -21,7 +21,7 @@ module dht11_interface #( localparam T_51US = CLK_FREQ * 51 / 1_000_000; localparam T_50US = CLK_FREQ * 50 / 1_000_000; localparam T_49US = CLK_FREQ * 49 / 1_000_000; - localparam T_40US = CLK_FREQ * 40 / 1_000_000; + localparam T_41US = CLK_FREQ * 41 / 1_000_000; localparam T_28US = CLK_FREQ * 28 / 1_000_000; localparam T_26US = CLK_FREQ * 26 / 1_000_000; localparam T_20US = CLK_FREQ * 20 / 1_000_000; @@ -104,13 +104,13 @@ module dht11_interface #( WAIT_RESPONSE: begin timer <= timer + 1; if (sig_in == 0) begin - if (timer > T_20US && timer < T_40US) begin + if (timer > T_20US && timer < T_41US) begin timer <= 0; state <= RESPONSE_LOW; end else begin state <= ERROR; end - end else if (timer > T_40US) begin + end else if (timer > T_41US) begin state <= ERROR; end end diff --git a/Semaine_6/DHT11/src/verilog/dht11_model.v b/Semaine_6/DHT11/src/verilog/dht11_model.v index 22a8bb3..f5108ea 100644 --- a/Semaine_6/DHT11/src/verilog/dht11_model.v +++ b/Semaine_6/DHT11/src/verilog/dht11_model.v @@ -1,142 +1,140 @@ module dht11_model ( - inout wire data, // Ligne de données bidirectionnelle - input wire clk, // Horloge système (50 MHz) - input wire rst_n // Reset actif bas + inout wire data, // Ligne de données bidirectionnelle + input wire clk, // Horloge système (27 MHz) + input wire rst_n // Reset actif bas ); - // Paramètres pour les timings (basés sur une horloge de 50 MHz, période 20 ns) - localparam CLK_FREQ = 50_000_000; // 50 MHz - localparam START_LOW_TIME = 18_000 / 20; // 18 ms pour le signal de démarrage - localparam START_HIGH_TIME = 40_000 / 20; // 20-40 µs pour le relâchement - localparam RESPONSE_LOW = 80_000 / 20; // 80 µs pour la réponse basse - localparam RESPONSE_HIGH = 80_000 / 20; // 80 µs pour la réponse haute - localparam BIT0_LOW = 50_000 / 20; // 50 µs pour bit '0' - localparam BIT1_LOW = 70_000 / 20; // 70 µs pour bit '1' - localparam DATA_BITS = 40; // 40 bits de données + // Paramètres pour les timings (basés sur une horloge de 27 MHz, période ~37 ns) + localparam CLK_FREQ = 27_000_000; // 27 MHz + localparam CLK_PERIOD_NS = 37; // 37 ns + localparam T_START_LOW = (18_000_000 / CLK_PERIOD_NS); // 18 ms + localparam T_START_HIGH = (39_500 / CLK_PERIOD_NS); // 40 µs + localparam T_RESP_LOW = (80_000 / CLK_PERIOD_NS); // 80 µs + localparam T_RESP_HIGH = (80_000 / CLK_PERIOD_NS); // 80 µs + localparam T_BIT0_LOW = (50_000 / CLK_PERIOD_NS); // 50 µs pour bit '0' + localparam T_BIT1_LOW = (70_000 / CLK_PERIOD_NS); // 70 µs pour bit '1' + localparam T_BIT_GAP = (50_000 / CLK_PERIOD_NS); // 50 µs entre bits + localparam DATA_BITS = 40; // 40 bits de données - // États de la machine à états - localparam IDLE = 3'd0, - START = 3'd1, - RESPONSE = 3'd2, - SEND_DATA = 3'd3, - ENDED = 3'd4; + // États de la machine à états de Moore + localparam IDLE = 4'd0, + WAIT_START_LOW = 4'd1, + WAIT_START_HIGH= 4'd2, + RESPONSE_LOW = 4'd3, + RESPONSE_HIGH = 4'd4, + SEND_BIT_LOW = 4'd5, + SEND_BIT_HIGH = 4'd6, + END_TRANS = 4'd7; - reg [2:0] state, next_state; - reg [15:0] counter; // Compteur pour les timings - reg [5:0] bit_index; // Index du bit à envoyer - reg data_out; // Valeur de sortie sur la ligne data - reg data_oe; // Contrôle de l'output enable (1 = sortie, 0 = haute impédance) - wire data_in; // Valeur lue sur la ligne data + // Signaux internes + reg [3:0] state; // État actuel + reg [19:0] counter; // Compteur pour les timings (supporte jusqu'à 20 ms) + reg [5:0] bit_index; // Index du bit à envoyer + reg data_out; // Valeur de sortie sur la ligne data + reg data_oe; // Output enable (1 = sortie, 0 = haute impédance) + wire data_in; // Valeur lue sur la ligne data // Données simulées (exemple : humidité = 45.0%, température = 23.0°C) - reg [7:0] humidity_int = 8'h2D; // 45 en décimal - reg [7:0] humidity_dec = 8'h00; // 0 - reg [7:0] temp_int = 8'h17; // 23 en décimal - reg [7:0] temp_dec = 8'h00; // 0 - reg [7:0] checksum; // Checksum = sum des 4 octets - - reg [39:0] data_shift; // Registre pour les 40 bits de données + reg [7:0] humidity_int = 8'h2D; // 45 en décimal + reg [7:0] humidity_dec = 8'h00; // 0 + reg [7:0] temp_int = 8'h17; // 23 en décimal + reg [7:0] temp_dec = 8'h00; // 0 + reg [7:0] checksum; // Checksum + reg [39:0] data_shift; // Registre pour les 40 bits de données // Gestion de la ligne bidirectionnelle assign data = data_oe ? data_out : 1'bz; assign data_in = data; - // Calcul du checksum + // Calcul du checksum et préparation des données always @(posedge clk or negedge rst_n) begin if (!rst_n) begin checksum <= 8'h00; - end else begin - checksum <= humidity_int + humidity_dec + temp_int + temp_dec; - end - end - - // Concaténation des données à envoyer - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin data_shift <= 40'b0; end else begin + checksum <= humidity_int + humidity_dec + temp_int + temp_dec; data_shift <= {humidity_int, humidity_dec, temp_int, temp_dec, checksum}; end end - // Machine à états + // Logique séquentielle (machine à états de Moore) always @(posedge clk or negedge rst_n) begin if (!rst_n) begin state <= IDLE; - counter <= 16'b0; + counter <= 20'b0; bit_index <= 6'b0; data_out <= 1'b1; data_oe <= 1'b0; end else begin - state <= next_state; + counter <= counter + 1; // Incrément du compteur par défaut + case (state) IDLE: begin - counter <= 16'b0; + counter <= 20'b0; bit_index <= 6'b0; data_out <= 1'b1; data_oe <= 1'b0; + if (data_in === 1'b0) // Vérification explicite pour éviter X + state <= WAIT_START_LOW; end - START: begin - counter <= counter + 1; - data_out <= 1'b0; - data_oe <= 1'b1; - end - RESPONSE: begin - counter <= counter + 1; - if (counter < RESPONSE_LOW) begin - data_out <= 1'b0; - data_oe <= 1'b1; - end else begin - data_out <= 1'b1; - data_oe <= 1'b1; - end - end - SEND_DATA: begin - counter <= counter + 1; - if (counter == 0) begin - data_out <= 1'b0; // Début du bit (toujours bas) - data_oe <= 1'b1; - end else if (counter == (data_shift[39-bit_index] ? BIT1_LOW : BIT0_LOW)) begin - data_out <= 1'b1; // Fin du bit - data_oe <= 1'b1; - end else if (counter >= (data_shift[39-bit_index] ? BIT1_LOW + 50 : BIT0_LOW + 50)) begin - counter <= 16'b0; - bit_index <= bit_index + 1; - end - end - ENDED: begin + WAIT_START_LOW: begin + data_out <= 1'b1; + data_oe <= 1'b0; + if (data_in === 1'b1 && counter >= T_START_LOW) + state <= WAIT_START_HIGH; + else if (data_in === 1'b1) + state <= IDLE; // Signal de démarrage trop court + end + WAIT_START_HIGH: begin + data_out <= 1'b1; + data_oe <= 1'b0; + if (counter >= T_START_HIGH) + state <= RESPONSE_LOW; + end + RESPONSE_LOW: begin + data_out <= 1'b0; + data_oe <= 1'b1; + if (counter >= T_RESP_LOW) + state <= RESPONSE_HIGH; + end + RESPONSE_HIGH: begin + data_out <= 1'b1; + data_oe <= 1'b1; + if (counter >= T_RESP_HIGH) + state <= SEND_BIT_LOW; + end + SEND_BIT_LOW: begin + data_out <= 1'b0; + data_oe <= 1'b1; + if (counter >= (data_shift[39-bit_index] ? T_BIT1_LOW : T_BIT0_LOW)) + state <= SEND_BIT_HIGH; + end + SEND_BIT_HIGH: begin + data_out <= 1'b1; + data_oe <= 1'b1; + if (counter >= T_BIT_GAP) begin + counter <= 20'b0; + bit_index <= bit_index + 1; + if (bit_index + 1 < DATA_BITS) + state <= SEND_BIT_LOW; + else + state <= END_TRANS; + end + end + END_TRANS: begin + data_out <= 1'b1; + data_oe <= 1'b0; + counter <= 20'b0; + state <= IDLE; + end + default: begin + state <= IDLE; + counter <= 20'b0; data_out <= 1'b1; data_oe <= 1'b0; - counter <= 16'b0; end endcase end end - // Logique de transition des états - always @(*) begin - next_state = state; - case (state) - IDLE: begin - if (data_in == 1'b0) // Détection du signal de démarrage - next_state = START; - end - START: begin - if (counter >= START_LOW_TIME && data_in == 1'b1) - next_state = RESPONSE; - end - RESPONSE: begin - if (counter >= RESPONSE_LOW + RESPONSE_HIGH) - next_state = SEND_DATA; - end - SEND_DATA: begin - if (bit_index >= DATA_BITS) - next_state = ENDED; - end - ENDED: begin - next_state = IDLE; - end - endcase - end - endmodule \ No newline at end of file diff --git a/Semaine_6/DHT11/tests/verilog/tb_dht11.v b/Semaine_6/DHT11/tests/verilog/tb_dht11.v index 58723dc..39d2e38 100644 --- a/Semaine_6/DHT11/tests/verilog/tb_dht11.v +++ b/Semaine_6/DHT11/tests/verilog/tb_dht11.v @@ -6,13 +6,13 @@ module tb_dht11; always #18.5 clk = ~clk; // Génère une clock 27 MHz // === Registres === - wire io_dht11_sig; - reg dht11_start; - wire dht11_data_ready; - wire dht11_busy; - wire [7:0] dht11_temp_data; - wire [7:0] dht11_hum_data; - wire dht11_error; + wire io_dht11_sig; + reg dht11_start; + wire dht11_data_ready; + wire dht11_busy; + wire [7:0] dht11_temp_data; + wire [7:0] dht11_hum_data; + wire dht11_error; // === Simulation du module DHT11 === dht11_model dht11_model (