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Add ultrasonic sensor model and driver, update testbench and scripts

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This commit is contained in:
Gamenight77
2025-05-19 11:42:28 +02:00
parent 9755b1b0a3
commit 436edae734
17 changed files with 740 additions and 3 deletions
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9
Semaine_6/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -56,7 +56,7 @@ module top_uart_ultrason_command (
reg [1:0] command = 0;
reg [31:0] delay_counter = 0;
reg [31:0] delay_counter = 13500000; // 0.5s
localparam US_STATE_WIDTH = $clog2(NEXT_FIFO)+1;
reg [US_STATE_WIDTH-1:0] mesure_state = IDLE;
@@ -65,6 +65,8 @@ module top_uart_ultrason_command (
if (data_available) begin
command <= rd_data[1:0];
leds <= rd_data[7:2];
end else begin
command <= 0;
end
end
@@ -97,7 +99,7 @@ module top_uart_ultrason_command (
CONTINUOUSSTART: begin
if (command == 3) begin
mesure_state <= NEXT_FIFO;
rd_en <= 1;
rd_en <= 0;
end else begin
mesure_state <= CONTINUOUSSTOP;
start <= 1;
@@ -111,8 +113,9 @@ module top_uart_ultrason_command (
end
WAIT: begin // Compteur 0.5s
if (delay_counter > 1) begin
if (delay_counter > 32'd1) begin
delay_counter <= delay_counter - 1;
mesure_state <= WAIT;
end else begin
mesure_state <= CONTINUOUSSTART;
delay_counter <= 13500000;