forked from tanchou/Verilog
Add ultrasonic sensor model and driver, update testbench and scripts
This commit is contained in:
Gamenight77
102
Semaine_6/ULTRASON/src/verilog/hc_sr04_model.v
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102
Semaine_6/ULTRASON/src/verilog/hc_sr04_model.v
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// Verilog model for single-pin ultrasonic sensor (e.g., HY-SRF05 in single-pin mode)
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// Simulates bidirectional pin for trigger/echo with internal random distance for testbenches
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// Author: Grok, xAI
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// Date: May 14, 2025
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module hc_sr04_model #(
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parameter CLK_FREQ_MHZ = 27 // Clock frequency in MHz (default 27MHz)
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) (
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input wire clk, // System clock
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inout wire sensor_pin // Bidirectional pin for trigger and echo
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);
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// Timing constants based on CLK_FREQ_MHZ
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localparam CLK_PERIOD_NS = 1000 / CLK_FREQ_MHZ; // Clock period in ns
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localparam TRIGGER_MIN_CYCLES = (10_000 / CLK_PERIOD_NS); // 10us minimum trigger pulse
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localparam CYCLE_TIME_CYCLES = (60_000_000 / CLK_PERIOD_NS); // 60ms cycle time
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localparam ECHO_DELAY_CYCLES = (1000 / CLK_PERIOD_NS); // 1us delay before echo (sensor processing)
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// State machine states
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localparam IDLE = 3'b000,
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CHECK_TRIGGER = 3'b001,
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ECHO_DELAY = 3'b010,
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ECHO_PULSE = 3'b011,
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WAIT_CYCLE = 3'b100;
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reg [2:0] state = IDLE;
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reg [31:0] counter = 0;
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reg sensor_pin_prev = 0;
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reg [31:0] random_distance = 0;
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reg [31:0] echo_cycles = 0;
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reg drive_echo = 0; // Controls when model drives sensor_pin
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// Calculate echo pulse width dynamically
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// Speed of sound: 343 m/s = 0.0343 cm/us
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// Echo duration (us) = 2 * distance (cm) / 0.0343 (cm/us)
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// Convert to clock cycles: duration (us) * 1000 / CLK_PERIOD_NS
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wire [31:0] echo_duration_us = (2 * random_distance * 1000) / 343; // Echo time in us
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wire [31:0] calculated_echo_cycles = (echo_duration_us * 1000) / CLK_PERIOD_NS; // Echo time in cycles
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// Bidirectional pin control: drive sensor_pin only during echo pulse
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assign sensor_pin = drive_echo ? 1'b1 : 1'bz;
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// Main state machine
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always @(posedge clk) begin
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// Store previous sensor_pin value for edge detection
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sensor_pin_prev <= sensor_pin;
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case (state)
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IDLE: begin
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drive_echo <= 0;
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counter <= 0;
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if (sensor_pin ) begin // Rising edge of trigger
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random_distance <= $urandom_range(2, 400); // Generate random distance
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state <= CHECK_TRIGGER;
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end
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end
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CHECK_TRIGGER: begin
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counter <= counter + 1;
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if (!sensor_pin) begin // Trigger pulse ended
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if (counter >= TRIGGER_MIN_CYCLES) begin
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$display("HC-SR04: Random distance = %0d cm at time %0t", random_distance, $time);
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echo_cycles <= calculated_echo_cycles; // Sample echo duration
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state <= ECHO_DELAY;
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counter <= 0;
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end else begin
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state <= IDLE; // Trigger too short
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end
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end
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end
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ECHO_DELAY: begin
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counter <= counter + 1;
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if (counter >= ECHO_DELAY_CYCLES) begin
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state <= ECHO_PULSE;
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drive_echo <= 1; // Start driving sensor_pin
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counter <= 0;
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end
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end
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ECHO_PULSE: begin
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counter <= counter + 1;
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if (counter >= echo_cycles) begin
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drive_echo <= 0; // Stop driving sensor_pin
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state <= WAIT_CYCLE;
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counter <= 0;
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end
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end
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WAIT_CYCLE: begin
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counter <= counter + 1;
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if (counter >= CYCLE_TIME_CYCLES) begin
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state <= IDLE;
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counter <= 0;
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end
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end
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default: state <= IDLE;
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endcase
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end
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endmodule
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154
Semaine_6/ULTRASON/src/verilog/ultrason_driver.v
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154
Semaine_6/ULTRASON/src/verilog/ultrason_driver.v
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@@ -0,0 +1,154 @@
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module ultrason_driver #(
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parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
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)(
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input wire clk,
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input wire start,
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inout wire sig, // Broche bidirectionnelle vers le capteur
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output reg [15:0] distance, // Distance mesurée en cm
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output reg busy,
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output reg done
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);
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reg [15:0] trig_counter = 0;
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reg [31:0] echo_counter = 0;
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reg [31:0] echo_div_counter = 0;
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reg [15:0] distance_counter = 0;
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reg sig_out;
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reg sig_dir; // 1: output, 0: input
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assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
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reg sig_int, sig_ok;
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localparam IDLE = 3'd0,
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TRIG_HIGH = 3'd1,
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TRIG_LOW = 3'd2,
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WAIT_ECHO = 3'd3,
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MEASURE_ECHO = 3'd4,
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COMPUTE = 3'd5,
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DONE = 3'd6,
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WAIT_NEXT = 3'd7;
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reg [2:0] state = IDLE;
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localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
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localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
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localparam integer MAX_CM = 350;
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localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
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localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
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reg [31:0] wait_counter;
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always @(posedge clk) begin
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sig_int <= sig;
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sig_ok <= sig_int;
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end
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always @(posedge clk) begin
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busy <= (state != IDLE);
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end
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always @(posedge clk) begin // FSM
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case (state)
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IDLE: begin
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done <= 0;
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sig_out <= 0;
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sig_dir <= 0;
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distance <= 0;
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if (start) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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done <= 0;
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end
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end
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TRIG_HIGH: begin
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sig_out <= 1;
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sig_dir <= 1;
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if (trig_counter < TRIG_PULSE_CYCLES) begin
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trig_counter <= trig_counter + 1;
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end else begin
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trig_counter <= 0;
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state <= TRIG_LOW;
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end
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end
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TRIG_LOW: begin
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sig_out <= 0;
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sig_dir <= 0; // Mettre en entrée
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if (sig_ok) begin
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state <= TRIG_LOW;
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end else
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state <= WAIT_ECHO;
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end
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WAIT_ECHO: begin
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if (sig_ok) begin
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echo_counter <= 0;
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state <= MEASURE_ECHO;
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end else if (echo_counter >= TIMEOUT_CYCLES) begin
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distance <= 0;
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state <= DONE;
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end else begin
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echo_counter <= echo_counter + 1;
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end
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end
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MEASURE_ECHO: begin
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if (sig_ok) begin
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if (echo_counter < TIMEOUT_CYCLES) begin
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echo_counter <= echo_counter + 1;
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end else begin
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state <= DONE;
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end
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end else begin
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state <= COMPUTE;
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end
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end
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COMPUTE: begin
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if (echo_counter >= DIST_DIVISOR) begin
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echo_counter <= echo_counter - DIST_DIVISOR;
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distance_counter <= distance_counter + 1;
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state <= COMPUTE;
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end else begin
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distance <= distance_counter;
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state <= DONE;
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end
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end
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DONE: begin
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if (start) begin
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wait_counter <= 0;
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state <= WAIT_NEXT;
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end else begin
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state <= IDLE;
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end
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done <= 1;
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end
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WAIT_NEXT: begin
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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distance_counter <= 0;
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echo_counter <= 0;
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end
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end
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default: begin
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state <= IDLE; // Reset to IDLE state in case of an error
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end
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endcase
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end
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endmodule
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152
Semaine_6/ULTRASON/src/verilog/ultrasonic_fpga.v
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152
Semaine_6/ULTRASON/src/verilog/ultrasonic_fpga.v
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@@ -0,0 +1,152 @@
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module ultrasonic_fpga #(
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parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
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)(
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input wire clk,
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input wire start,
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inout wire sig, // Broche bidirectionnelle vers le capteur
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output reg [15:0] distance, // Distance mesurée en cm
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output reg busy,
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output reg done
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);
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reg [15:0] trig_counter = 0;
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reg [31:0] echo_counter = 0;
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reg [31:0] echo_div_counter = 0;
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reg [15:0] distance_counter = 0;
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reg sig_out;
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reg sig_dir; // 1: output, 0: input
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assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
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reg sig_int, sig_ok;
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localparam IDLE = 3'd0,
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TRIG_HIGH = 3'd1,
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TRIG_LOW = 3'd2,
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WAIT_ECHO = 3'd3,
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MEASURE_ECHO = 3'd4,
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COMPUTE = 3'd5,
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DONE = 3'd6,
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WAIT_NEXT = 3'd7;
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reg [2:0] state = IDLE;
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localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
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localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
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localparam integer MAX_CM = 350;
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localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
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localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
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reg [31:0] wait_counter;
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always @(posedge clk) begin
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sig_int <= sig;
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sig_ok <= sig_int;
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end
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always @(posedge clk) begin
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busy <= (state != IDLE);
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end
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always @(posedge clk) begin // FSM
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case (state)
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IDLE: begin
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done <= 0;
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sig_out <= 0;
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sig_dir <= 0;
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distance <= 0;
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if (start) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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done <= 0;
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end
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end
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TRIG_HIGH: begin
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sig_out <= 1;
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sig_dir <= 1;
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if (trig_counter < TRIG_PULSE_CYCLES) begin
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trig_counter <= trig_counter + 1;
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end else begin
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trig_counter <= 0;
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state <= TRIG_LOW;
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end
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end
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TRIG_LOW: begin
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sig_out <= 0;
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sig_dir <= 0; // Mettre en entrée
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if (sig_ok) begin
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state <= TRIG_LOW;
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end else
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state <= WAIT_ECHO;
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end
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WAIT_ECHO: begin
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if (sig_ok) begin
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echo_counter <= 0;
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state <= MEASURE_ECHO;
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end else if (echo_counter >= TIMEOUT_CYCLES) begin
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distance <= 0;
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state <= DONE;
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end else begin
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echo_counter <= echo_counter + 1;
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end
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end
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MEASURE_ECHO: begin
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if (sig_ok) begin
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if (echo_counter < TIMEOUT_CYCLES) begin
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echo_counter <= echo_counter + 1;
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end else begin
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state <= DONE;
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end
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end else begin
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state <= COMPUTE;
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end
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end
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COMPUTE: begin
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if (echo_counter >= DIST_DIVISOR) begin
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echo_counter <= echo_counter - DIST_DIVISOR;
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distance_counter <= distance_counter + 1;
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state <= COMPUTE;
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end else begin
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distance <= distance_counter;
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state <= DONE;
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end
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end
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DONE: begin
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if (start) begin
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wait_counter <= 0;
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state <= WAIT_NEXT;
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end else begin
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state <= IDLE;
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end
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done <= 1;
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end
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WAIT_NEXT: begin
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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distance_counter <= 0;
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echo_counter <= 0;
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end
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end
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default: begin
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state <= IDLE; // Reset to IDLE state in case of an error
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end
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endcase
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end
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endmodule
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