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Refactor FIFO module: update pointer and count handling for improved functionality

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Louis TANCHOU
2025-05-22 14:49:36 +02:00
parent 54bf6df85b
commit 4c3e40b266
4 changed files with 95 additions and 13 deletions
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13
Semaine_6/DHT11_UART/src/verilog/dht11_uart_top.v
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@@ -43,10 +43,11 @@ dht11_interface dht11_inst (
);
// === FSM ===
localparam WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
reg [2:0] state = WAIT;
localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
reg [2:0] state = X;
reg [31:0] delay_counter = 0;
reg strobe2s = 0;
reg [7:0] data_fifo = 30;
// 2s counter
always_ff @(posedge clk) begin
@@ -61,6 +62,12 @@ end
always_ff @(posedge clk) begin
case (state)
X: begin
i_start <= 0;
wr_en <= 1;
wr_data <= data_fifo;
state <= WAIT;
end
WAIT: begin
i_start <= 0;
wr_en <= 0;
@@ -72,7 +79,7 @@ always_ff @(posedge clk) begin
MESURE: begin
i_start <= 0;
if (o_dht11_data_ready && !o_busy) begin
if (o_dht11_data_ready) begin
state <= SEND_FIFO1;
wr_data <= o_temp_data;
wr_en <= 1;