Refactor FIFO module: update pointer and count handling for improved functionality

Semaine_5/DHT11_UART/scripts/build copy.bat

@@ -0,0 +1,45 @@
+@echo off
+setlocal
+
+rem === Aller à la racine du projet ===
+cd /d %~dp0\..
+
+rem === Config de base ===
+set DEVICE=GW2AR-LV18QN88C8/I7
+set BOARD=tangnano20k
+set TOP=top_uart_ultrason_command
+set CST_FILE=%TOP%.cst
+set JSON_FILE=runs/%TOP%.json
+set PNR_JSON=runs/pnr_%TOP%.json
+set BITSTREAM=runs/%TOP%.fs
+
+rem === Créer le dossier runs si nécessaire ===
+if not exist runs (
+    mkdir runs
+)
+
+echo === Étape 1 : Synthèse avec Yosys ===
+yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+if errorlevel 1 goto error
+
+echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
+nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
+if errorlevel 1 goto error
+
+echo === Étape 3 : Packing avec gowin_pack ===
+gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
+if errorlevel 1 goto error
+
+echo === Étape 4 : Flash avec openFPGALoader ===
+openFPGALoader -b %BOARD% %BITSTREAM%
+if errorlevel 1 goto error
+
+echo === Compilation et flash réussis ===
+goto end
+
+:error
+echo === Une erreur est survenue ===
+
+:end
+endlocal
+pause

Semaine_6/DHT11_UART/IP/verilog/fifo.v

@@ -12,10 +12,12 @@
     output wire             empty
 );
 
+    localparam LOGSIZE = $clog2(SIZE);
+
     reg [WIDTH-1:0]         fifo[0:SIZE-1];
-    reg [3:0]               wr_ptr;
+    reg [LOGSIZE-1:0]               wr_ptr;
-    reg [3:0]               rd_ptr;
+    reg [LOGSIZE-1:0]               rd_ptr;
-    reg [3:0]               count;
+    reg [LOGSIZE:0]               count;
 
     assign full = (count == SIZE);
     assign empty = (count == 0);
@@ -27,17 +29,20 @@
     end
 
     always @(posedge clk) begin // IN
-        if (wr_en && !full) begin
+        rd_data <= fifo[rd_ptr];
+        if (wr_en && !full && rd_en && !empty)  begin
             fifo[wr_ptr] <= wr_data;
-            wr_ptr <= (wr_ptr + 1) % SIZE;
+            wr_ptr <= (wr_ptr == SIZE - 1) ? 0 :  (wr_ptr + 1) ;
+            rd_ptr <= (rd_ptr == SIZE - 1) ? 0 :  (rd_ptr + 1) ;
+        end else if (wr_en && !full) begin
+            fifo[wr_ptr] <= wr_data;
+            wr_ptr <= (wr_ptr == SIZE - 1) ? 0 :  (wr_ptr + 1) ;
             count <= count + 1;
-        end
+        end else if (rd_en && !empty) begin // OUT
-
+            rd_ptr <= (rd_ptr == SIZE - 1) ? 0 :  (rd_ptr + 1) ;
-        if (rd_en && !empty) begin // OUT
-            rd_data <= fifo[rd_ptr];
-            rd_ptr <= (rd_ptr + 1) % SIZE;
             count <= count - 1;
         end
+
     end
     
 endmodule

Semaine_6/DHT11_UART/scripts/linux/upload.sh

@@ -0,0 +1,25 @@
+#!/bin/bash
+
+# Aller à la racine du projet
+cd "$(dirname "$0")/../.." || exit 1
+
+# Config de base
+DEVICE="GW2AR-LV18QN88C8/I7"
+BOARD="tangnano20k"
+TOP="dht11_uart_top"
+CST_FILE="$TOP.cst"
+JSON_FILE="runs/$TOP.json"
+PNR_JSON="runs/pnr_$TOP.json"
+BITSTREAM="runs/$TOP.fs"
+
+# Créer le dossier runs si nécessaire
+mkdir -p runs
+
+echo "=== Étape 4 : Flash avec openFPGALoader ==="
+sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
+if [ $? -ne 0 ]; then
+  echo "=== Erreur lors du flash ==="
+  exit 1
+fi
+
+echo "=== Compilation et flash réussis ==="

Semaine_6/DHT11_UART/src/verilog/dht11_uart_top.v

@@ -43,10 +43,11 @@ dht11_interface dht11_inst (
 );
 
 // === FSM ===
-localparam WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
+localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
-reg [2:0] state = WAIT;
+reg [2:0] state = X;
 reg [31:0] delay_counter = 0;
 reg strobe2s = 0;
+reg [7:0] data_fifo = 30;
 
 // 2s counter
 always_ff @(posedge clk) begin
@@ -61,6 +62,12 @@ end
 
 always_ff @(posedge clk) begin
     case (state)
+        X: begin
+            i_start <= 0;
+            wr_en <= 1;
+            wr_data <= data_fifo;
+            state <= WAIT;
+        end
         WAIT: begin
             i_start <= 0;
             wr_en <= 0;
@@ -72,7 +79,7 @@ always_ff @(posedge clk) begin
 
         MESURE: begin
             i_start <= 0;
-            if (o_dht11_data_ready && !o_busy) begin
+            if (o_dht11_data_ready) begin
                 state <= SEND_FIFO1;
                 wr_data <= o_temp_data;
                 wr_en <= 1;